2
\$\begingroup\$

Question: enter image description here Positive half-cycle: D1 ON, D2,D3 OFF
Negative half-cycle: D3 ON, D2 OFF(Vin>=-4V), D2 ON(Vin<-4V), D1 OFF
First positive half-cycle is not steady state.
Considering from the first negative half-cycle after Vin <-4V,

enter image description here Correction: The above AC Voltage source's shape would be triangle not sine.

V(c) = 0-(-4) = 4V , Vo = 0V
For positive half-cycle the capacitor can be replaced by a 4V battery.: enter image description here

Vo = 10V.
Output waveform: enter image description here Have I done it correctly?

\$\endgroup\$
  • \$\begingroup\$ Is that supposed to be a sine? Or a triangle? (You left the "sine" word on a schematic.) \$\endgroup\$ – jonk Jul 24 '17 at 16:54
  • 1
    \$\begingroup\$ Just out of curiosity, have you attempted to draw out the node voltage over time for the node just to the left of the capacitor, without considering the following capacitor and diode? \$\endgroup\$ – jonk Jul 24 '17 at 17:05
  • \$\begingroup\$ that would be triangle I missed it while drawing the schematic . @jonk \$\endgroup\$ – Utshaw Jul 24 '17 at 17:06
  • 1
    \$\begingroup\$ And one more question for you. Do you need to show a diagram of the output for the next triangle cycle? (It might be different than the first.) \$\endgroup\$ – jonk Jul 24 '17 at 17:09
  • \$\begingroup\$ yes I need to show . I thought it would be the same \$\endgroup\$ – Utshaw Jul 24 '17 at 17:10
3
\$\begingroup\$

Let me redraw your schematic:

schematic

simulate this circuit – Schematic created using CircuitLab

It's a lot easier to recognize this way. The diodes are arranged to cause clipping at the common node shared by \$D_1\$, \$D_2\$, \$R_1\$, and \$C_1\$ -- namely \$V_a\$.

The following "graph" shows you the input voltage in blue and the \$V_a\$ node voltage in red:

schematic

simulate this circuit

Note that it follows the input voltage until one, or the other, diode conducts. At which time, it stays at the appropriate battery voltage on the other side of that diode. This means that the positive peak is at \$+6\:\textrm{V}\$ and the negative peak is at \$-4\:\textrm{V}\$. This is the clipping effect at node \$V_a\$.


Now, there is missing information from your problem: the initial voltage across the capacitor. But when a problem doesn't state it, then we can fairly argue that it is uncharged and has zero volts across it.

As a consequence of this "assumption," for the first cycle only the voltage on the other side (right side) of your capacitor should "follow" the curve in red shown above. That is, if there wasn't a diode present at the output. But there is. So this is yet another problem to consider.

If you examine the red curve above and assume that there is no voltage across the capacitor, then the output will be able to follow the positive portion of the red curve since the output diode is reverse-biased.

That portion does not look like the curve you provided.

On the negative portion of the red curve, however, the diode is forward biased and therefore conducts. This means that the output is prevented from going more negative (in the ideal-diode case) than zero volts.

That portion does look more like the curve you provided. (Not entirely, though, as we'll soon see.)


However, there's more.

While the red curve reaches its most negative peak value of \$-4\:\textrm{V}\$, the capacitor's voltage is fully charged up to that difference, since the diode is conducting and holding the output to zero volts.

Therefore, immediately at the point where the red curve's voltage begins rising back up towards zero volts, the capacitor will have its left side negatively charged (which was just at \$-4\:\textrm{V}\$, relative to its right side (which was just at \$0\:\textrm{V}\$.) So as the red curve moves back upwards on that final leg, the capacitor voltage will add to it. Because of the capacitor polarity, this will add \$+4\:\textrm{V}\$ to the final leg of the red curve.

As the last final leg of the red curve rises upward, the output will be \$+4\:\textrm{V}\$ higher (meaning it will rise above zero volts) and the output diode will cease to conduct (it will be off.) Therefore the output will rise upward with the last leg of the red curve, but \$+4\:\textrm{V}\$ higher.


This should be more than sufficient information for you to compose a final output diagram for the first cycle.


However, there is still more.

Now. If you are supposed to provide the steady-state case, after the capacitor gets a charge from the first cycle, the answer will be a little different. From your comments that I now see, you do need to show the next cycle (or steady-state case.)

So you need to follow up by realizing that after the first cycle the capacitor will be charged up. Apply this knowledge to the red curve I provided but now with the added voltage to it.

Note that node \$V_a\$ will still look the same in the next cycle (verify this in your own mind.) However, now you will have a charged capacitor to deal with in working out what \$V_{out}\$ looks like.

See where that takes you.

\$\endgroup\$
  • \$\begingroup\$ So , the charged capacitor will force the output diode to be turned off for the last leg of the negative half-cycle ? @jonk \$\endgroup\$ – Utshaw Jul 24 '17 at 18:38
  • \$\begingroup\$ @Utshaw No, because you have a pass-through capacitor before the diode. It will pass only the AC part, and the diode will limit the voltage in such way nothing goes negative. The diode will slide the graphic up, so the lowest point is zero. The red curve drawn by jonk moves 4V upwards. \$\endgroup\$ – Todor Simeonov Jul 24 '17 at 18:41
  • \$\begingroup\$ @Utshaw Just as Todor said! Yes! (If you are just looking at the last leg of the red curve.) Now, on the NEXT CYCLE? Different things take place because now the capacitor has been charged. \$\endgroup\$ – jonk Jul 24 '17 at 18:55
  • \$\begingroup\$ My Answer The black arrow is my desired output voltage. During Leg L1, D3 diode is ON , So , it will be 0V. During this time , the capacitor will be charged.L2 will be clamped by 4V.Then L3 will be stuck on 6+4 = 10V.Then L4 will be clamped by 4V too due to the chanrged capacitor.Note: When the V(input) > -4V there will be insufficient voltage for turning ON the D3 diode as the capacitor is charged now(It will oppose turning ON D3 diode).After V(input) < -4V then D3 will be ON (& charging up the capacitor too).L6 will be just 4V clamped due to the charged capacitor. \$\endgroup\$ – Utshaw Jul 25 '17 at 2:47
  • \$\begingroup\$ Is it okay now? \$\endgroup\$ – Utshaw Jul 25 '17 at 2:52

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.