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This is an update to my previous board here, which I made after implementing the useful suggestions offered in that post.

In the schematic I have added decoupling capacitors, programming header and a pullup resistor to the RESET pin. I have also removed the loading caps on the RTCs crystal as it was not needed.

The wire of the label is not being displayed in Eagle (idk whats wrong but no time to figure it out right now). Please take note of the following pins:

PB3 - MOSI
PB4 - MISO
PB5 - SCK
PC6 - RESET

Now onto the board. In the board I have used a ground pour on both sides. I used a simple trace to route VCC to all the required parts, because I was having some difficulty with a VCC polygon. Now I surrounded the crystal with the ground plane as best as I could. The vias around the crystal connect the bottom and top ground planes.

So once again, suggestions are needed. Also I have 2 questions:

  1. Can someone please check if I connected the decoupling capacitors correctly in the board.
  2. There are three vias that are coming under the TQFN package of the AVR. Now the production house I use does make copper filled vias so the connection will be ensured. I want to ask will it be fine soldering the chip on top.

I am looking forwards to your feedback. Thanks a lot.

EDIT:I modified it to move the decoupling capacitors closer to the pins. But the problem is that now the crystal is a little further away. I don't know if this will cause any problems. enter image description here

PS: Ignore the silkscreen for now, I will clear it up later. Schematic Board

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    \$\begingroup\$ If you're done with the other question, please accept an answer so that it won't keep popping up back again. If you are not, then you should add this as an update instead of a new question. \$\endgroup\$ – Wesley Lee Jul 25 '17 at 15:58
  • \$\begingroup\$ p.s.: if you had a given problem in the other design and "solved" it badly in this new one, you'll have duplicate answers pointing out the same problem... \$\endgroup\$ – Wesley Lee Jul 25 '17 at 15:59
  • \$\begingroup\$ If your board shop doesn't do plated thru-holes.... find another vendor..... \$\endgroup\$ – Trevor_G Jul 25 '17 at 15:59
  • \$\begingroup\$ Why are all your decoupling caps 100pF ? is that a mistake ? I think you meant for 100nF. \$\endgroup\$ – Mike Jul 26 '17 at 3:36
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There are three vias that are coming under the TQFN package of the AVR. Now the production house I use does make copper filled vias so the connection will be ensured. I want to ask will it be fine soldering the chip

Is it QFN or TQFP?

In both cases, if the chip does not have a thermal pad in the center (seems like this is true), then of course you can put vias under the chip. You don't need any via fill or anything special. It's just a via.

Can someone please check if I connected the decoupling capacitors correctly in the board.

Nope, there is a problem.

Get rid of the useless copper fill on top layer. Its only purpose is to worsen ground routing and coupling between traces. Now, you can almost put a solid ground plane on the back. In fact, I'm pretty sure you can route everything on toplayer.

The caps are supposed to be placed close to the power pins they decouple. Not at the end of a long trace like C1/C2...

If this will be hand soldered, you cap put the caps in the bottom layer too.

Also, check the traces going to JP_LCD. This connector would be much better in the top left corner.

There are no mounting holes.

You should add a bulk cap, like an aluminium electrolytic, for supply decoupling.

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  • \$\begingroup\$ Its a TQFP. Sorry 'bout that. Yes I will hand solder this so can I place the caps at the bottom and connect them with vias? \$\endgroup\$ – hacker804 Jul 25 '17 at 16:14
  • \$\begingroup\$ Also, if I get rid of the top ground pour, will that not cause problems for the crystal? \$\endgroup\$ – hacker804 Jul 25 '17 at 16:15
  • \$\begingroup\$ OK, if you have trouble fitting the caps on top, put'em on the bottom. You can put the VCC via under the chip, makes routing easier for the other pins. Your XTAL will work fine without top ground pour (there is a ground plane on the bottom after all). \$\endgroup\$ – peufeu Jul 25 '17 at 16:46
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I still strongly suggest you move c3 and c4.

enter image description here

They should be on the inside as shown below, and keep those two traces as short as you can.

enter image description here

You might also want to double check the landing pattern on that crystal. The pads look a lot wider than the device itself.

ALSO

Unless you have a specific reason for the orientation, I would consider rotating that layout or moving JP_LCD to shorten all those traces.

Your decoupling caps should be as close to the power pins of the device they are associated with as you can make them. Having them half a board away is pointless.

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  • \$\begingroup\$ Do crystal load caps have to be on the clock path? I was under impression, that they serve as an additional load, not decouplers, hence it's not really mandatory to move them. \$\endgroup\$ – stiebrs Jul 26 '17 at 10:56
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    \$\begingroup\$ @stiebrs they are not decouplers, however you need to keep the crystal traces as short as possible. In this layout putting them inboard on the crystal does not extend the trace. Putting them on the left you add a couple of extra trace stubs that are not necessary. Worse, you actually add a couple if little antennas that way. \$\endgroup\$ – Trevor_G Jul 26 '17 at 11:46
  • \$\begingroup\$ Crystal load caps should return directly and only to the nearest AVR ground pin. Allowing other paths is a great way to create a transmitter on the crystal harmonics. The cap values should be the specified crystal load capacitance times two, minus 5 or 6 pf for stray C. So a 22pF crystal needs (22*2)-6 or 38pF \$\endgroup\$ – user103218 Jul 26 '17 at 18:58

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