Hi I'm a computer science student doing a computer hardware course and am having trouble understanding this circuit which is supposed to show how control signals at the memory can be generated using this address decoding circuit.

enter image description here

The explanation of the diagram is: "The generation of the necessary control signals at the memory is shown in the following circuit, which is an address decoding circuit. It decodes the address to generate individual control signals to the different memory locations. When READ is active(0), READ0 is active(0) if ADDRESS is 0, and READ1 is active if ADDRESS is 1. The write control signals are similarly activated".

Would someone mind helping me understand how this circuit works? I know that the 4 gates on the right are OR gates and that to give an active output only one of their inputs needs to be active.


2 Answers 2


It may help to write out the boolean logic.

!Read0 = Address + !Read
!Read1 = !Address + !Read
!Write0 = Address + !Write
!Write1 = !Address + !Write

Now, apply DeMorgan's Law.

Read0 = !Address & Read
Read1 = Address & Read
Write0 = !Address & Write
Write1 = Address & Write

If your address is low, and you're in read mode, Read0 is asserted. If your address is high, and you're in read mode, Read1 is asserted. If your address is low, and you're in write mode, Write0 is asserted. If your address is high, and you're in write mode, Write1 is asserted.

So address selects 1 or 0, and read and write behave as expected.


The tricky thing about the circuit is all of the negated signals. If you construct a logic truth table for the inputs and output of each if the gates, you will see how the circuit works. I assume this is homework, so I'm only going to do one for you, and let you figure out the rest.

I can't put bars over the negated signals, so I am using a leading ! instead.

For the top OR gate:

Address  !Read   !Read0

   0       0       0
   0       1       1
   1       0       1
   1       1       1

So you can see that the output !Read0 will only be active (0) if Address is 0 and !Read is 0. For all other cases, !Read0 will be 1.

Note that the truth table above is the same as a NAND gate with inverted inputs, which is equivalent to an OR gate by DeMorgan's Theorem:

enter image description here

BTW the schematic is poorly drawn, there should be dots where the signals are actually connected, and no dots where the lines simply cross each other. It is possible to make out what the intent is here, but for a more complicated circuit it would be impossible.


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