I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a FPGA of the Cyclone II family.
From my simulation it results that a II order FIR using a direct adders can be clocked at higher frequency than a II order FIR using transposed adders (420Mhz vs 387Mhz). I did not expect this given that the critical path of the direct is bigger (2sum+1mult) than the one of the transposed (1s+1m).
Is this due to the fact that the direct has a more parallel architecture than the transposed and so the FPGA 'likes' this? img1) direct img2) transposed