# FPGA maximum frequency : limiting factor

I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a FPGA of the Cyclone II family.

From my simulation it results that a II order FIR using a direct adders can be clocked at higher frequency than a II order FIR using transposed adders (420Mhz vs 387Mhz). I did not expect this given that the critical path of the direct is bigger (2sum+1mult) than the one of the transposed (1s+1m).

Is this due to the fact that the direct has a more parallel architecture than the transposed and so the FPGA 'likes' this? img1) direct img2) transposed

I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams).

Because your multiplying coefficients are all powers of 2, your multiplies can all be done by simple bit selects. For example, assuming you're doing 16-bit math, x*0.25 can be calculated as simply {2'b0, x[15:2]} (using Verilog notation).

This means your multiplications with positive coefficients are essentially free, and require no time at all.

Multiplying by a negative coefficient, however, means making a 2's-complement calculation, requiring inverting the bits and adding 1. That "adding 1" step implies a carry chain with delay equivalent to an adder of the same width.

So now you're effectively comparing two systems that both have a critical path equivalent to two adders, and it's down to luck which one happens to synthesize with less delay.

If you're using SystemVerilog or some other higher-level synthesis tool, the tool might even notice that one of the sums in the first version can be pipelined (calculated one clock cycle in advance) and thus reduce the critical path to a single adder.

• Thanks for your answer, I had that suspect too and so I tried to implement the first one (LPF) with the second architecture and it resulted that the max clock fq were the same (420vs387 again) so I concluded that the operation makes no difference but the problem is another one. I implemented the multiplication(or rather divisions) in vhdl with a bit-shift (and the +1 when negative). You gave me some food for thought, thanks. – AM93 Jul 26 '17 at 17:52
• @AM93, note my last paragraph. Your first form can be changed from $0.25 x + 0.5 x z^{-1} + 0.25 x z^{-2}$ to $0.25 x + (0.5 x + 0.25 x z^{-1})z^{-1}$, reducing the critical path to a single adder (and neglecting any difference in overflow behavior). – The Photon Jul 26 '17 at 17:59

There are many, many paths in an FPGA, and of course, the slowest limits the overall speed.

Many of these paths are sensitive to your particular design. Many are unfortunately dependent on the placing that the placer/router has managed to achieve, so it's quite common for a design that has been running at some frequency suddenly drops in frequency when some quite insignificant (you think) extra piece is added.

Each FPGA vendor will employ craft to speed up this or that design. If your layout matches one of layouts they optimised well, if you're riding the horse in the direction it's going, then you will get a fast design. If not, then extra switches and fanouts and lines will need to be employed, reducing the speed.

Because FPGAs are so complex, it's beyond the wit of most people to figure out exactly what the speed is going to be ahead of layout, you just have to run it and see, and gain experience. Generally, register to register with little intermediate processing is going to be the fastest, but you knew that already.