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I am very new to FPGA development, but I have a relatively simple application I'm trying to implement on a Microsemi ProASIC3. The hardware I have to work with has no external clock source (i.e., no crystal or resonator). At first, I assumed there was some way to generate an independent internal clock, as you can with some microcontrollers, but reading through the datasheet this doesn't appear to be something this family can do (indeed, reading the internet, it seems to not be a feature of most FPGAs).

For this application, there isn't strictly a need for a clock - nothing is time-driven. The FPGA is simply maintaining an internal register that corresponds with a bunch of outputs. This register's value changes depending on the present state of some inputs and some internal logic.

But, looking at the various FPGA resources I see that clocks are fairly ubiquitous in example designs. While I'm fairly confident that I don't need one - I fear that half way through development I will find a need for one will arise in some unexpected place.

My question is: should I throw out this hardware and get something with a clock onboard, because clocks are effectively required for all designs and I'm wasting my time working without one? Or is it entirely possible to build sensible FPGA designs that never need external clocking?

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    \$\begingroup\$ Performing a purely combinatorial FPGA design would be highly unusual. You really won't be able to leverage a lot of the capabilities - for example, things like block rams are inherently synchronous (=require a clock). \$\endgroup\$ – Chris Stratton Jul 27 '17 at 2:37
  • \$\begingroup\$ @ChrisStratton is correct for pure FPGA ....many of the features such as RAM blocks do need clocks since they are synchronous logic blocks. However there are alternatives that span the asynchronous world such as Lattice's MachX02 which provides PLD/CPLD capability. The smaller MachX02 is particularly great for asynch logic and has async SRAM blocks you can use as registers. There are a bunch of examples of async logic on the Lattice site: latticesemi.com/en/Products/FPGAandCPLD/MachXO2.aspx ...so you can design programmable logic without clock domains. \$\endgroup\$ – Jack Creasey Jul 27 '17 at 5:12
  • \$\begingroup\$ @alexandicity you can build FGPA's without clocks, but the propagation delay will make designs unusable. Delays add up, the constant switching will draw power, its a bad idea \$\endgroup\$ – Voltage Spike Jul 27 '17 at 6:00
  • \$\begingroup\$ This particular model claims several "clock conditioning circuit" blocks and an optional PLL, are you sure it's not capable of clock generation? \$\endgroup\$ – pjc50 Jul 27 '17 at 8:17
  • \$\begingroup\$ Thanks all. Looks like I will have a headache if this implementation grows beyond anything but the most basic design. Looks like I should get an external clock and avoid future stress! @PJC50: The CCC seem to be just to alter and modify an external clock, not to replace it. \$\endgroup\$ – alexandicity Jul 27 '17 at 19:11
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If you need a clock inside FPGA, you can synthesize an internal ring oscillator, see an example here. If totally internal, there might be some implementation caveats, it might be either optimized out, or too fast and unstable. However, if you can sacrifice two I/O pins on your hardware platform, you can put a RC delay there, and close the loop internally.

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    \$\begingroup\$ How do you do the static timing analysis (STA) for such a design? How does STA consider timing variations? \$\endgroup\$ – Paebbels Jul 27 '17 at 6:05
  • \$\begingroup\$ Hi Ali - thanks for the idea. The answer there also mentions that ring oscillators are a bad idea, for reasons that are quite understandable (indeed, the ones you say). I'd like to avoid getting into bad habits if I can :) As for the RC circuit - well, I'd probably just opt for a crystal in this case. \$\endgroup\$ – alexandicity Jul 27 '17 at 16:01
  • \$\begingroup\$ @alexandicity, I guess the spectrum of answers regarding ring oscillators depends on individual skillset and experience. Many ICs do have ring oscillators to keep the logic functional in low-power states, so the oscillator should be modeled in FPGA RTL. Again, "a crystal" likely won't work, and you will need a "crystal oscillator chip". If your design doesn't require precise timing for some sensitive serial interfaces, a correctly-designed ring oscillator is a way to go. \$\endgroup\$ – Ale..chenski Jul 27 '17 at 16:42
  • \$\begingroup\$ @Paebbels, a ring oscillator has certain working range of frequencies. You just do you timing analysis for the highest frequency it can deliver. And with external RC you should have a pretty good idea what the upper limit is. \$\endgroup\$ – Ale..chenski Jul 27 '17 at 16:44
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I found an app note that discusses creating a ring oscillator on the ProASIC 3L series parts: https://www.microsemi.com/document-portal/doc_view/129924-ac332-flash-freeze-control-using-an-internal-oscillator-app-note . That might be a decent option if it's not possible to add an external oscillator.

Many FPGAs contain internal ring oscillators that are used during startup to load the configuration. On many Xilinx FPGAs, it is possible to get access to this signal and use it as a clock in a design.

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