-3
\$\begingroup\$

I need to design a counter circuit that counts in 5-bit binary form between the numbers (0-31) by 5 using only logic gates without any programming. when the counter reaches 30 it must go as 3..8..13.. as next loop and so on..I'm thinking of using D-type FF's and full adders for this purpose. But after a lot of searching I could not apply it yet! I have a simulation file that does that circuit job successfully and exactly as I want..but I cannot understand how does the circuit work? Could you please explain to me how this circuit is working? and what are the roles of plugged full adders? how it can be possible to design another circuit doing the same count pattern? https://drive.google.com/open?id=0B7bJDDDSwTBCeEpLb0RZOTkxaW8

The simulation was done by Logicly.

Clarification: the counting will be like: 0..5..10..15..20..25..30..3..8..13..18..23..28..1..6..11..16..21..26..31..4..9..14..19..24..29..2..7..12..17..22..27..0.. in a 5-bit binary form ( 5 LEDs can be used as an output representation)

Here are screenshots for the simulation: project full adders structures :
4-bit full adder full adder

\$\endgroup\$
  • \$\begingroup\$ "it must go as 3..8..13.. as next loop and so on"?????????? Probably nobody is going to download your file. \$\endgroup\$ – Andy aka Jul 27 '17 at 10:00
  • \$\begingroup\$ I wrote additional explanation. \$\endgroup\$ – utdlegend Jul 27 '17 at 10:05
  • \$\begingroup\$ I think it can be interesting for some people to see such a circuit..I hope someone download and see it! \$\endgroup\$ – utdlegend Jul 27 '17 at 11:12
  • \$\begingroup\$ The problem with your .logicly file is that it requires one to also download and install a commercial program in order to view it. Please at least show us a screenshot here. \$\endgroup\$ – Dave Tweed Jul 27 '17 at 11:20
  • \$\begingroup\$ Screenshots are uploaded! \$\endgroup\$ – utdlegend Jul 27 '17 at 11:34
2
\$\begingroup\$

One way to tackle this is to simply design a five bit counter with standard binary counting sequence and then put logic gates that take the five output bits and translate those to the five outputs of the desired count sequence. The below truth table shows this. The green part of the table shows the binary bits from the counter that are the inputs to the translator gates. The red part of the table shows the desired output bits. For each red column create a 32 cell Karnaugh map from the input bits states to derive the minimum logic gate circuit for each output.

enter image description here

Once you understand how this process works you can approach a more proper design where instead of using a binary front end counter simply have those be five flip-flops that hold the current value of the 5-step count and use a similar bank of logic gates to produce the next state value to load into the flops at each clock pulse.

The truth table for the "proper" design is as follows where the greens represent the inputs to logic gates that decode next state from the current state. The red columns represent the next state gate outputs that feed back into the D inputs of the flip-flops. Again use a 32-cell Karnaugh map to find the minimum logic for each of the red columns.

Just to make it clear I have no intention to do the final solution of your homework......just showing how to organize your information into how a solution is produced.

enter image description here

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.