I have an application where I suspect the main overhead is accessing L3 cache. It is run on a modern Intel server-grade microprocessor with a huge L3 cache. There are many microprocessors available with various core counts and frequencies, and selecting between these is hard.
So, that led me to wonder whether L3 cache access (hit) time scales down with frequency. So, if 2GHz CPU accesses L3 cache in e.g. 12 ns, does that mean that a 3GHz CPU accesses L3 cache in 8 ns? Of course, this may depend on internal implementation details of the CPU, so let's limit answers to modern i386/AMD64 microprocessors.
I know that at least in the case of DRAM the delays are practically constant, so if you do a random DRAM access, higher frequency means only better sequential data rate after the random access penalty has been paid. But is SRAM fundamentally different? It is based on transistors, so I guess it could be clocked at pretty good frequencies.
Sorry if this is the wrong place to ask, there is no better place to ask detailed computer architecture questions. I have considered CS StackExchange and StackOverflow, but I think Electrical Engineering StackExchange was the best place. There really should be a Computer Architecture StackExchange but there isn't!