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I am looking at the following PCB (single layer).

enter image description here

The checked red/blue is GND.

  1. Can this polygon give EMI problems in the sense that it acts as an antenna because it does not form a closed loop ?

  2. Should polygons be closed loop ?

  3. On a signal layer board, is there any reason to have ground/vcc pours on unused copper areas ?

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  • \$\begingroup\$ Do you have an EMI problem? I've seen EMI problems (PCBs that failed testing at 200--500MHz) because of long traces between MCUs and analog frontend ICs, that were undampened. Adding 1Kohm, or 10KOhm, near the analog IC, solved the problem. \$\endgroup\$ – analogsystemsrf Jul 27 '17 at 17:43
  • \$\begingroup\$ @analogsystemsrf I don't have a problem (yet). 1kohm between what and what ? \$\endgroup\$ – efox29 Jul 27 '17 at 18:45
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Can this polygon give EMI problems in the sense that it acts as an antenna because it does not form a closed loop ?

Yes, at high enough frequencies, that long "peninsula" of copper can act as an antenna, causing radiation, or capturing interference from external signals.

Should polygons be closed loop ?

Loops isn't really what you're aiming for, but it would be better to put some vias through the polygon to tie it tightly to the ground plane on an inner layer beneath it.

On a signal layer board, is there any reason to have ground/vcc pours on unused copper areas ?

In manufacturing, large "glass" areas (areas without copper) slightly increase costs, because they deplete the etchant more quickly.

As far as performance benefits, if your traces are not controlled impedance and you have an unbroken ground plane on an inner layer, I don't see much benefit to these copper pours.

If your traces are controlled impedance and intended to be microstrip, you probably need to increase the gap between the trace and the ground pour to maintain the correct characteristic impedance. A gap of 3 - 5x the trace width is preferred.

If your traces are controlled impedance coplanar waveguide, then of course you need the copper pours to form the return path for currents on those traces. But you also need to be sure the pour is fully connected to the end of the trace, and you need a pour on both sides of each trace.

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    \$\begingroup\$ In this case, its a single layer board (there are no other inner or out planes). Vias are not possible, so is there an advantage to having closed loop polygons vs no polygon ? \$\endgroup\$ – efox29 Jul 27 '17 at 14:34
  • \$\begingroup\$ Haven't done many single-layer boards. But I'd still think loops are not the goal. What you want is to be sure there's a return path for every power trace and every signal. And probably limit your signal rise & fall times to minimize radiation. \$\endgroup\$ – The Photon Jul 27 '17 at 15:27
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Can this polygon give EMI problems in the sense that it acts as an antenna because it does not form a closed loop ?

Islands are bad because they add another element of unpredictability, they are hard to analyze. There exists capacitance between the traces around them and the ground plane below. The capacitance between the island and the trace depends on the length of the trace running next it. It is less time consuming to remove the island or ground it than it is to model it with a basic model or 3d EM FEM to find out if it is a problem.

Should polygons be closed loop ?

They should be grounded so you know what the potential is. Multiple vias can lower inductance to ground and also help as vias have high frequency impedance

On a signal layer board, is there any reason to have ground/vcc pours on unused copper areas?

Maybe, remember two conductors with an electric field running between them form a capacitor. PCB's can create many opportunities for parasitic capacitance, although small and usually negligible, any two conductors can have capacitance between them. There are PCB calculators to get an idea for what these values are, or equations.

This capacitance can create problem, or solve them. If it makes sense to ground or attach a small capacitor (<1pf usually, but some plane to plane capacitance can be much more) to your trace then ground the copper underneath it.

Here is an example of how to look at traces and capacitance between them (in your case there would also be a plane next to the trace with another capacitor drawn to the plane and and additional capacitor from the plane to ground)

enter image description here
Source Bert Simonovich's Design Notes

There is also mutual inductance between traces, but that mostly applies to traces that are run together for a given distance and is a story for another day.

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You went through the trouble of separating your signal traces, presumably to reduce crosstalk.

Then you add a copper pour between them, which will increase crosstalk through capacitive coupling...

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  • \$\begingroup\$ If I have the space, I always separate. Unfortunately, I do not have a reference plane below since its a single layer board (ie only only side has copper). \$\endgroup\$ – efox29 Aug 1 '17 at 14:04
  • \$\begingroup\$ Come on, you can get double sided cheaper than happy meal these days... \$\endgroup\$ – peufeu Aug 1 '17 at 19:01
  • \$\begingroup\$ A happy meal is way to expensive for this project. High volume...500k-1M...cents matter. \$\endgroup\$ – efox29 Aug 1 '17 at 19:04
  • \$\begingroup\$ Ha! Understood. What kind of frequencies are involved here? \$\endgroup\$ – peufeu Aug 1 '17 at 20:10

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