Interpreting the open loop gain of a linear power supply

This question is related to a question asked earlier regarding a linear power supply build. It turns out that the circuit is oscillating quite badly; an issue not uncommon in feedback circuits. I've been researching compensation techniques in order to cure the problem and, as an introduction, I've found this tutorial series to be very helpful.

It doesn't deal with my situation exactly (which is to be expected) but (thanks to its intuitive approach), I've been able to create a simulation model in spice that attempts to help me understand the open loop frequency response, which is also as the text explains, the loop gain Ab when the closed loop gain is unity.

The original Farnell power supply on which this circuit is based can be found here and you can see from the spice model image below that I haven't changed much from the original.

In order to find the OL response, I've removed any negative feedback (including the original local compensation) and tied the inverting input to control ground (0V). Then running the AC analysis, I get the following:

If I understand the result correctly, the response across the entire frequency domain is attenuated. If this is true and I'm doing this correctly, how can this circuit ever really oscillate? Since according to the tutorial mentioned above, the circuit is unstable (at unity gain) when the gain at f(-180 degrees) is greater than 1.

UPDATE:

Fix suggested by Andy, some local feedback to equalize the inputs (but not enough to affect the response at FOI):

With open loop AC response 100Hz to 1GHz:

• Apologies to reviewers, I had made a slight error in my simulation which gave an incorrect AC analysis result. Images corrected now and the question still stands. – Buck8pe Jul 28 '17 at 13:54
• You have to also look at the phase, if you delay your feedback enough it will always be different than the intended value. – PlasmaHH Jul 28 '17 at 13:55

If this is true and I'm doing this correctly, how can this circuit ever really oscillate?

You're not doing it correctly. The TL082 has an input offset voltage of a few milli volts and, no doubt, this will be present in the sim model so, you need to find a way of cancelling that offset at the input so that the op-amp's output is not hitting against one of the power rails and producing virtually no output signal at all.

This is both a real-life and a sim problem.


If you are careful, you can provide local DC negative feedback to keep it biased correctly without disturbing what happens close to the higher frequencies where instability naturally happens in this type of circuit.

Alternatively, do an analysis of just the transistor stages and see how the phase changes at the higher-end frequencies. Add this phase-shift piecemeal to the graphed open loop response in the data sheet and all should be revealed. For instance: -

The TL082 op-amp should produce a 90 degree phase shift all the way from 100 Hz to about 1 MHz and this tells you that above 1 MHz, you might expect to see problems develop when you add the effects from all the output transistors.

However, above 3 MHz the gain of the TL082 is less than one and, because those added transistor don't introduce any gain, you know that the likely hot-spot is between 1 MHz and 3 MHz.

If you are intent on using the complete circuit may I recommend that you operate the op-amp locally with a DC gain of about 3,000. This will completely unaffect the response at 10 kHz or above but will give you the DC operating conditions necessary to make the simulator work. See this: -

To the graph above I've added a red-line indicating that if you fed your sim input via a 1 kohm resistor to the inverting input and used a 3 Mohm negative feedback resistor local to the op-amp you would be fine. Now though, you need to connect the non-inverting input terminal to mid-rail/ 0 volts.

Even if you forced a local dc gain of -100 you will be unlikely to overlap with any areas that might be unstable.

• Right. That makes sense. So, what you're saying is that you need to introduce negative feedback to make the inputs balance but with an insignificant phase contribution that allows you to look at the "outer" feedback loop (and also the compensating feedback loop when it's present) for margin, right? – Buck8pe Jul 28 '17 at 14:10
• Correct @Buck8pe – Andy aka Jul 28 '17 at 14:12
• Well, that's interesting because the frequency of oscillation I was seeing was around 150kHz (see previous question)?? I'm guessing that's because of the local compensation I already have from the original circuit (680k in series with 1nF). – Buck8pe Jul 28 '17 at 14:20
• Yes, that local compensation could throw my numbers out easily by an order of magnitude. – Andy aka Jul 28 '17 at 14:26
• I've updated the question to include the fix for the bias, as I understand it. Do I have this right? – Buck8pe Jul 28 '17 at 15:06

You are not taking the gain of the opamp into account. The rest of the system is a glorified emitter follower, so will have a gain a little below 1. However, the opamp supplies a huge gain.

To fix the overall circuit, put a little local compenstation immediately around the opamp. Try 100 pF directly from the opamp output to its negative input, and make sure that there is enough impedance driving the negative input for the capacitor to work against.

• There's a bit of a story behind all this and basically my prototype does have local compensation, as you describe. However, it was designed for the original circuit (which I have changed somewhat). I wanted to take a "systematic" approach to computing a new value for the compensation network. – Buck8pe Jul 28 '17 at 14:14

AC analysis in spice is based on a linearization of the DC operating point. When you break the loop you no longer have a valid DC operating point. In this case your error amplifier is railed.

One solution to this problem is to dominant pole compensate the loop with a sub-hertz pole. The low-pass filter below has zero attenuation at DC (assuming the input impedance to your error amplifier is large). However it blocks frequencies down into the uHz. The end result is a valid DC operating point. The response from VTEST to V(FB) is the open-loop gain.

simulate this circuit – Schematic created using CircuitLab

EDIT: Sample loop gain simulation

A simplified schematic of your circuit above to illustrate where to inject AC stimulus for loop gain analysis. Note this circuit is uncompensated (crossing 0dB at 40 dB/dec is the dead giveaway).

The resulting open-loop gain simulation is the following,

The response at the V(cntrl) node is the exclusively the open-loop gain of the opamp (Aol: 100dB, GBW: 1MHz, phi: 60 deg). The response at the V(out) node is the complete open-loop gain of the simplified circuit.

• I think I get what you're saying (although I had to read it 10 times:-) ). You're saying don't break the loop, instead arrange it so that the loop filters out (practically) all AC and thus provides a DC level. Have I got that right? – Buck8pe Jul 28 '17 at 14:46
• Exactly, with the RC filter the gain completely around the loop is zero for practical AC values. However the gain from your test stimulus to output of your circuit is the behavior in open-loop. As no signals pass through the RC filter (at least within frequencies of interest). – sstobbe Jul 28 '17 at 14:57
• Note that FB goes to the output of the amplifier and not the input. – Andy aka Jul 28 '17 at 17:58
• Actually, I'm finding it hard to model this one in the context of what I have. Any chance you could re-work your schematic to include an op amp so I can see what goes where - exactly? – Buck8pe Jul 28 '17 at 18:12
• @Buck8pe please see edits for a sample loop gain simulation – sstobbe Jul 28 '17 at 19:18