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Here is shown the design of simple multi-staged amplifier.

schematic

simulate this circuit – Schematic created using CircuitLab

I tried to put together all three NPN transistor configurations and this is what I got - just redrawn schematic of each individual configuration connected together.

First I was hoping for optimal power transition between stages and that was meant to be achieved by proper impedance matching between the output and input of each individual stage. Then I tried to achieve desired voltage gain of each stage (with formulas shown later). When I was calculating voltage gain of each stage individually I did consider the ohmic resistance of next stage that was "loading" the first stage (or the stage for which voltage gain was to be calculated).

I set the amplitude of function generator on the value of only 10mVpp, so the output voltage wouldn't be clipped at the first place. The power supply DC voltage was high enough too, so the clipping could be avoided. Maybe you will be wondering why are values of last stage voltage divider so low (which is not usual for a voltage divider) - as I have said, certain input/output impedance formulas needed to be matched for optimal power transition + 14.4V drop across R1''' and 15.6V drop across R2''' (which is also not usual for voltage divider).

  • Circuit was observed by oscilloscope (analog) and the resulting amplitude of loaded amplifier was a disaster - output was greatly distorted; not clipped but distorted in many different ways. So my question is: Where did I went wrong on this one?

I should also note that calculated loaded voltage gain calculus of each individual stage had very unrealistic values - voltage gain of whole circuit was somewhere about 80k...

This was also my first multi-staged amplifier ever made, so I must admit I was very disappointed upon the results.

Here are listed formulas used in this "amplifier" design process:

enter image description here

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$ – Dave Tweed Jul 29 '17 at 10:57
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    \$\begingroup\$ Let me just summarize, I guess. Your 1st stage and 2nd stage need some additional design work and/or a topology change. Your 3rd stage isn't really all that workable, because an emitter follower (without crazy extremes) just cannot function very well to drive a speaker (for reasons you don't yet follow, I gather.) Perhaps you can provide a different post to chop this up into steps. \$\endgroup\$ – jonk Jul 29 '17 at 17:35
  • \$\begingroup\$ @jonk Just tell me, if there is any practical use of formulas that I provided in my question? \$\endgroup\$ – Keno Jul 30 '17 at 15:32
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    \$\begingroup\$ @Keno Just having formulas tells you nothing about when they apply and when they don't (their boundary conditions and application space.) The difference is like the difference between someone looking at cooking recipes and imagining they can take some of this from one recipe and some of that from another recipe and make something that works in the end; and a cook who knows how chemistry and flavors work, in theory, and can be told to do something new and can achieve it through the proper use of theory. But to answer you, yes, there is practical use for at least some formulas in some cases. \$\endgroup\$ – jonk Jul 30 '17 at 17:55
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Normally when I start the design process I start at the last stage.

For example, let us assume that you want 1Vpeak across the load. The peak load currents is 0.25A.

So, the emitter follower Q3 current need to be larger than this 0.25A (the large the better).

Let me set Ie3 = 0.4A. and Re3 = 15V/0.4A = 39Ω (I ignore the power dissipation for now).

So because of this large current, we are a force to use a power BJT.

schematic

simulate this circuit – Schematic created using CircuitLab

Also, I decided to use a Darlington stage, to reduce the loading effect.

The voltage the Q1 base must be around \$ 0.5Vcc + 2Vbe = 16.3V\$ and the voltage divider current larger than \$Idiv >\frac{0.4A}{\beta_1*\beta_3} = \frac{0.4A}{1000} = 0.4mA\$ at least 5 to 10 times larger.

$$R_3 = \frac{16.3V}{2mA} = 8.2kΩ$$ $$R_2 = \frac{30V - 16.3V}{2mA + 0.4mA} = 5.6kΩ$$

$$ C_O >\frac{0.16}{F*R_L} =\frac{0.16}{20Hz *4\Omega} = 2200\mu F $$

Now, the first stage. I assume a gain around 50V/V.

The Darlington stage emitter follower input resistance is

$$Rin2 = R_2||R_3||(\beta_1*\beta_3 * (re+R_{e3}||R_L)) \approx 1.8kΩ$$

As you can see \$Rin2\$ is low which is not good. CE stage don't like to drive low resistance load.

Normally \$Rc2 < \frac{Rin2}{10}\$ but I decided to pick \$Rc2 = 510\Omega\$

The collector current is:

$$Ic = \frac{15V}{510\Omega} = 30mA$$

For good thermal stability i select \$Re2 = \frac{2V}{30mA} = 68\Omega \$

Hence \$V_e = 30mA*68\Omega = 2.04V\$ and \$V_B = 2.04V + 0.7V = 2.74V\$

The base current is around \$I_B = 0.3mA \$ so the voltage divider current around 3mA.

$$R_8 = \frac{2.74V}{3mA} = 1k\Omega$$

$$R_7 = \frac{30V - 2.74V}{3mA + 0.3mA} = 8.2k\Omega$$

So, to be able to achieve the voltage gain in the range of a 50V/V, the emitter resistance for AC signal must be smaller than:

$$\frac{Rc||Rin2}{Av} = \frac{510Ω||1.8kΩ}{50} \approx 7.9Ω$$

The "build in" emitter resistance is

$$re1 =\frac{V_T}{I_C}= \frac{26mV}{30mA} = 0.87\Omega$$

This is why I add additional resistor (R9) into emitter in series with Ce capacitor.

$$Rx = (7.9\Omega - 0.87\Omega) \approx 7\Omega $$

$$R_9 = \frac{7\Omega * 68\Omega}{68\Omega - 7\Omega} = 7.5\Omega$$

Now have to pick the capacitors value.

$$C_e = \frac{0.16}{20Hz*7.5\Omega} = 1000\mu F$$

$$C_2 = \frac{0.16}{20Hz* (1.8k\Omega+510\Omega)} = 4.7\mu F$$

$$Cin = \frac{0.16}{20Hz* (R7||R7||(\beta*R_9))} = 2.2\mu F$$

Additional we have to check the power dissipation in BJT's and in the resistor.

And the emitter follower will clip for negative half cycle at

\$0.4A * Re3||R_L = -1.45Vpeak\$

As you can see Class A amplifiers are not very economical. This is why you will never see this kind of a circuit in a modern amplifier.

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  • \$\begingroup\$ Do you think the Co is needed? To eliminate DC component? \$\endgroup\$ – Keno Jul 29 '17 at 21:46
  • \$\begingroup\$ @Keno In general, the loudspeaker or the headphones do not like the DC voltage/current and this is why we need a Co capacitor in the circuit. \$\endgroup\$ – G36 Jul 29 '17 at 23:39
  • \$\begingroup\$ @Keno In the audio circuit, we don't match the impedance. R_Source = R_Load. Why? Because in the audio circuit the "signal" is the voltage. Hence, for maximum voltage transfer, the destination device (called the "load") should have an impedance of at least ten times that of the sending device (called the "source") R_Source < 10*R_Load (simple voltage divider) \$\endgroup\$ – G36 Jul 30 '17 at 9:24
  • \$\begingroup\$ I know that now. But for a loudspeaker not only voltage matters; sometimes the current has to be amplified on a higher level that the source can supply. In that case, probably the best thing you can use is Darlington transistor pair, right? \$\endgroup\$ – Keno Jul 30 '17 at 9:44
  • \$\begingroup\$ @Keno In a typical audio power amplifier, the last stage (some kind-of an emitter follower douglas-self.com/ampins/dipa/dpafig13.gif ) is to "amplify" the current. And typical it is a complementary emitter follower (push-pull stage) with Darlington pairs. electronics.stackexchange.com/questions/309936/… \$\endgroup\$ – G36 Jul 30 '17 at 10:10
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Congratulations on this excellent learning experience. Seriously.

With 10 millivolts into any diode, or emitter of a common-base, or base of a common-emitter[with no emitter R], you'll get serious distortion. I'd expect obvious imbalance of the sinusoid swings positive versus negative. If I recall right, 4mVpp causes 10% distortion. You are 10mVpp.

If I understand the schematic (its a bit fuzzy), stage 1 has gain of ~~ 60X. Stage 2 has gain of 1,000x.

With 60,000X gain, that 0.01volt input becomes 600volts PP output.

Major cause of distortion is that output stage. With 100 Ohm pulldown, the going-low drive ability is too weak for 4 Ohm speaker. With the emitter not able to "follow" the base, the input resistance varies greatly, causing 2:1 change in load of the prior CE stage and causing 2:1 amplitude variation as sinusoid tries to swing positive and then negative.

Also your 3rd stage CC is dissipating 1.5 watts in the Re, and 2/3 watt in each base resistor.

Major cause of frequency rolloff is the input capacity of middle stage. I'd expect Rc (stage1) and Cin = device_Cob * StageGain (10pF * 1,000x = 0.01uF) to produce Tau = R * C = 3,000 ohms * 0.01uF = 0.3 milliSeconds, 3,333 radians per second or 3,333/6.28 = 500 Hertz F3dB. Not good for even voice.

To exploit the huge gain of stage 2, try this (cascoded, to reduce Miller Effect from 1,001 to 1+2=2

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Stage 1 looks like a voltage gain of 50 to me; stage 2 looks more like about 20ish to me. (The capacitor impedance at 1 kHz is quite high compared to little-re, which also means the output is not going to be anywhere near 180 degrees out of phase.) So I don't get anywhere near your max gain figure, though I can see where you got yours. In any case, the whole design by the OP is beyond any simple repair. Needs global feedback or, if open loop with only local degeneration in each stage, then a different arrangement. \$\endgroup\$ – jonk Jul 29 '17 at 6:02
  • \$\begingroup\$ Right. I ignored the "matching between stages", including the DC_blocking caps. The matching introduces 6dB attenuation at each interface. \$\endgroup\$ – analogsystemsrf Jul 29 '17 at 16:52

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