In VHDL, does having large bus input to component take extra resources?

Question

I have a component that has a very large array signal in it (a couple kilobits) and I currently write and read to it in only one component. I have checked in Vivado if this uses too much resources, and it doesn't. My question is I want to have a sub-component that can access this array (only read from it). If I merely set the array as an input to the sub-component, will it take any more resources that if I implemented the array in the same component? I know the optimizing compiler is pretty powerful, but I don't know what goes on when you interface between VHDL components.

Thanks

Answer 1

When you look at the design as a schematic, you might get a false sense that borders exist between your individual modules (or entities). But, by default Vivado flattens your design - which means your design is essentially treated as one big layout. All sub-component boundaries are ignored. So, just think of it as if you had simply copied the sub-component's code and pasted it into the parent.

Of course, you can tell Vivado to maintain your defined hierarchy (i.e. not flatten the design), in which case the place and routing stages will try and colocate the guts of each individual entity within the fabric. But even still, it won't replicate drivers of signals which exist in parent components.

Answer 2

When you have a large array in HDL design (whether VHDL or Verilog) the synthesizer will often recognise it as a "ram" and implement it using block ram rather than a huge pile of registers.

However it can only do this in a limited subset of cases, if it can't map it to a ram you will end up with a huge pile of registers. In particular most rams only have two "ports", so reading or writing your array from more than two places (whether in the same module or not) is almost certain to land you up with a pile of registers.

I do not know if the inferring of block ram happens before or after the design is flattened, you would have to experiment to find that out.

Finally be very careful when testing partial designs. It's all too easy to end up with large parts of your design synthesized away completely because you didn't connect its output to anything or because you fed it's input with a constant.

Answer 3

[Competely rewritten answer, because I misunderstood the question.]

From a synthesis point of view, a signal that is an array is equivalent to a bunch of separate signals for each element. Synthesis will generally deal with each of those separate signals independently.

Synthesis will own require interconnect resources between the driver (source) of a particular signal, in this case each array component, and the synthesized logic that uses that signal as an input (sinks). Just passing the signal around at the VHDL source code level via VHDL component ports only defines the connectivity in a purely logical sense, but does not specific that those signals have any particular routing path and resources as synthesized.

Specifically, if the large array signal is driven in one component, and passed via a port to another component, every individual signal element will have to be routed from its own source to its own sink(s), but each of those will be routed separately in as minimal a way as the synthesis and P&R can do it.