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The excerpt below is from ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters.

On page 2, introduction section:

The electrical performance of a dc to dc converter depends, to a large extent, on the quality of its control system. Unfortunately, most single-loop approaches suffer from many inherent limitations:

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  • The long time constant associated with the low-pass filter delays the rate of power-switch-modulation adjustment responding to a dynamic line and/or load disturbance, thus compromising the converter dynamic response.

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What is time constant in LC circuit? I know time constant in RC, RL circuits but the time constant in LC circuit is somewhat strange to me.
Can anyone explain it?

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What is time constant in LC circuit?

In the context of the paper you linked on switching converters, it is the response time introduced by the filter that causes problems. Basically it's the transient response time: -

enter image description here

It is made more complex because the load can change and thus the damping ratio can change so it is difficult to know how long the output may take to get to within (say) 5% of its final settling point.

Because it is inside a feedback loop, instabilities can occur if not properly managed. When considered from the frequency domain, the RLC low pass filter can rapidly introduce a 180 degrees phase shift over a short span of frequencies from just below resonance to just above resonance: -

enter image description here

If you took the dotted-green curves as an example it appears to be roughly "butterworth" in shape and at 50% resonance it introduces a phase shift of about 35 degrees whereas at twice resonance this has shifted to about 145 degrees. This can easily cause instability if not properly managed.

In short, I believe they actually mean "time delay to reasonably settle" rather than the time constant associated with a simple RC network.

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I think what they refer to in the paper is the cutoff frequency of the \$LC\$ filter in a buck converter for example. The transfer function of such a filter can be approximated by a second-order polynomial form: \$H(s)=\frac{1}{1+\frac{s}{Q\omega_0}+\left(\frac{s}{\omega_{0}}\right)^2}\$ if we neglect the ohmic losses. The ripple voltage you get on the output (considering a low ESR) directly depends on the high-frequency response of the \$LC\$ filter whose transfer function, in high-frequency, can be approximated to \$H(s)\approx(\frac{\omega_0}{s})^2\$. By simple manipulations, you can link the ripple amplitude \$\Delta V\$ with the \$LC\$ filter cutoff frequency \$f_0\$ as the following expression shows: \$\frac{\Delta V}{V_{out}}=\frac{\pi^2}{2}(\frac{f_0}{F_{sw}})^2(1-D)\$ derived in here. By adjusting the cutoff frequency with respect to the switching frequency \$F_{sw}\$, you can select the amount of ripple you accept. Obviously, reducing the cutoff frequency will induce the lowest output ripple but will force you to place compensation zeros close to \$f_0\$ with the consequence of slowing down the transient response. Reducing \$f_0\$ can also be seen as growing the \$L\$ component if size constraints impose a small capacitor. You know that inductance opposes current variations so by growing \$L\$, you hamper the converter response time as inductive current cannot grow faster than what V-s authorize. For all of these reasons, most of the time, people designing buck converters starts with the selection of an inductive ripple current (30-40% of \$I_{L,avg}\$ seems a sweet spot) and select the output capacitor with \$f_0\$ and the ripple spec. Later on, it is very likely that the capacitor ESR dictates the final ripple amplitude and imposes the choice of a different capacitor. Most of these comments apply to other converters as well: in a nutshell, small \$L\$ means higher ripple but authorizes fast current variations (high-bandwidth converters) whereas a large inductance certainly reduces the ac ripple but leads to a slow converter at the end. Hope this answers the question.

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Series RLC

\$Q=\dfrac{\omega _oL}{R}=\dfrac{1}{\omega _oCR}~~~~~\$

Parallel RLC

\$~~Q=\dfrac{R}{\omega _oL}=\omega _oCR\$

where \$|Z_L|={\omega L}\text{ = } |Z_c|=\dfrac{1}{\omega C}\$ and \$\omega _o=\dfrac{1}{\sqrt {LC}}\$

Since \$Q=\dfrac{f_o}{f_{(-3dB)~~~}}\$

If we a step function input with an underdamped oscillation at \$f_o\$ and the -3dB bandwidth relates the time constant of the envelope decay until it is steady, the time delay of the envelope is similar to the T=RC time constant.

Can you figure it out from here? (using RLC) ( if I haven't made a serious blunder )

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An LC circuit never settles, so there is no transient period and 'time constant' does not apply.

For a standard 2nd order TF with damping (e.g. resistance), time constant is usually approximated by: \$\tau\approx\large\frac{1}{\zeta\omega_n}\$, but this measure doesn't have a lot of relevance if \$ \small\zeta<1\$.

In the case of a series RLC circuit, for example, \$\small\zeta=\frac{R}{2}\sqrt{\frac{C}{L}}\$, and \$\omega_n=\frac{1}{\sqrt{LC}}\$, giving \$\tau=\frac{2L}{R}\$.

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