How do you implement the following sort of functionality in VHDL that is synthesizable?

USE IEEE.std_logic_1164.all;

ENTITY memory IS
    PORT (
        data : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) := (OTHERS => 'Z');
        write : IN STD_LOGIC;
        trigger: IN STD_LOGIC;
        ack: OUT STD_LOGIC := '0'
END memory;

    SIGNAL memory: STD_LOGIC_VECTOR (23 DOWNTO 0) := (OTHERS => '0');
    PROCESS (trigger)
        IF rising_edge(trigger) THEN
            IF write='0' THEN
                memory <= data;
                data <= memory;
            END IF;
            ack <= '1';
        ELSIF falling_edge(trigger) THEN
            data <= (OTHERS => 'Z');
            ack <= '0';
        END IF;
END logic;

but that doesn't work due to:

ERROR - memory.vhd(28): statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition. VHDL-1242
Done: error code 2

(Some arrangements I've tried synthesize but yield "register ack_NN stuck at ZERO" sort of errors which I assume mean they won't actually work as expected either.)

basically I want to create entities that can be connected to another entity and pass data in or out between them asynchronously. It seem you should be able to do this with some simple handshaking like "A has data for me" -> "copy data from A" -> "tell A I'm done copying" -> "wait for "A" to see I'm done".

There's got be a way to transfer data in to/out of another entity asynchronously but I'm at loss to figure out how to do it. And it seems you should be able to do this without a clock which would just seem to turn this into a synchronous solutions. How do you accomplish this goal asynchronously?

  • \$\begingroup\$ See Why is this not synthesizable? (does not hold its value under NOT(clock-edge)) on Stackoverflow. You can't use both edges of trigger as a clock. There are specific forms for recognizing sequential logic for synthesis representing realizable hardware. \$\endgroup\$ – user8352 Jul 30 '17 at 0:46
  • \$\begingroup\$ Try doing all these WITHOUT using rising_edge and falling_edge that most synthesizers will try to do with a synchronous circuit. But keep this in mind: Asynchronous design is VERY tricky and most FPGA tools are thought for synchronous design. \$\endgroup\$ – Claudio Avi Chami Jul 30 '17 at 4:28

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