How do you implement the following sort of functionality in VHDL that is synthesizable?
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY memory IS PORT ( data : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) := (OTHERS => 'Z'); write : IN STD_LOGIC; trigger: IN STD_LOGIC; ack: OUT STD_LOGIC := '0' ); END memory; ARCHITECTURE logic OF memory IS SIGNAL memory: STD_LOGIC_VECTOR (23 DOWNTO 0) := (OTHERS => '0'); BEGIN PROCESS (trigger) BEGIN IF rising_edge(trigger) THEN IF write='0' THEN memory <= data; else data <= memory; END IF; ack <= '1'; ELSIF falling_edge(trigger) THEN data <= (OTHERS => 'Z'); ack <= '0'; END IF; END PROCESS; END logic;
but that doesn't work due to:
ERROR - memory.vhd(28): statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition. VHDL-1242 Done: error code 2
(Some arrangements I've tried synthesize but yield "register ack_NN stuck at ZERO" sort of errors which I assume mean they won't actually work as expected either.)
basically I want to create entities that can be connected to another entity and pass data in or out between them asynchronously. It seem you should be able to do this with some simple handshaking like "A has data for me" -> "copy data from A" -> "tell A I'm done copying" -> "wait for "A" to see I'm done".
There's got be a way to transfer data in to/out of another entity asynchronously but I'm at loss to figure out how to do it. And it seems you should be able to do this without a clock which would just seem to turn this into a synchronous solutions. How do you accomplish this goal asynchronously?