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I wand to design a headphone amplifier based on CFA topology (for some very personal aesthetic reason). There are two basic topologies of its input stage which is technically an V-I amplifier (I-V converter providing voltage gain is usually implemented via two current mirrors "fighting" each other). I want to know why one can be preferred to another. In both cases the design procedure is unclear for me. In particular how to choose resistors' values? I have some clues, but I'm not completely sure.

In case a) \$R1\$ and \$R2\$, I guess, provide some additional Vce room for \$Q3\$ and \$Q4\$.

Case b) should work well (and it does on simulation) without resistors at all. So, I guess, \$R3\$ and \$R4\$ may help to minimize some differences in \$Q5\$ and \$Q6\$ characteristics. But I have no clue how exactly. In case of non zero \$R3\$ and \$R4\$, \$R5\$ and \$R6\$ may serve for biasing purposes.

Shortly speaking, what is the purpose of emitter resistors in both these circuits?

Unfortunately I can't find any article which can explain the procedure. Can you point me to some?

Two primary CFA input topologies

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    \$\begingroup\$ I updated the image. Current sources here are just emitter followers loads. \$\endgroup\$ – e_asphyx Jul 30 '17 at 17:41
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    \$\begingroup\$ I prefer the first circuit. This connection keeps Vce almost constant( Q3 and Q4). So the Miller effect is reduced and improves the PSRR. Also, you should add resistors to Q3 and Q4 emitter also. And the optimal value for Re resistor lies around this value Re = 0.5 Vt/Ie = 13mV/Ie. Famous modified Olivier's criteria hpl.hp.com/hpjournal/pdfs/IssuePDFs/1971-02.pdf Page 11 \$\endgroup\$ – G36 Jul 30 '17 at 17:54
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    \$\begingroup\$ @jonk Lucky you. I was born in the 80's \$\endgroup\$ – G36 Jul 30 '17 at 18:14
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    \$\begingroup\$ @G36 Nah. Getting old is not "lucky." I'd gladly be born in the 1980's and not remember that computer. ;) [Even with gross overpopulation, climate change, and the sixth species extinction event in progress today.] \$\endgroup\$ – jonk Jul 30 '17 at 18:31
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    \$\begingroup\$ @e_asphyx . Yes, you are right. The Oliver condition is RE = VT/Ie and crossover distortion is minimized. But for CFA amplifier (complementary stage also work in class B) we get the lowest distortion when Re = 0.5*VT/Ie for perfectly matched PNP/NPN transistors. \$\endgroup\$ – G36 Jul 31 '17 at 13:10
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For case a: R1 and R2 stop thermal runaway when the Vbe of Q1 and Q2 decrease due to heating (Q1 and Q2 are usually the output transistors). The collectors of Q3 and Q4 could functionally be connected to the supply rails (in a similar fashion to Q7 and Q8) but are connected to the output for reduced power dissipation.

The main difference between the designs is turn off speed of the transistors that are intended to be the output transistors (Q1, Q2, Q5 and Q6).

Case A turns off Q1 and Q2 very well - stored charge is actively removed from the base of Q1 and Q2 via Q3 and Q4, assuming there is sufficient current sourcing capability of the input signal.

Case B has no means of removing the stored charge from the base of Q5 and Q6, so turn off will be very very slow. Usually there is a resistor from base to emitter of Q5 and Q6, but the value of these are a compramise between wasting current from the drive stage before it and speed of charge removal from the base of the transistor.

As a side note, the current mirror output is a questionable approach unless you load your "in-" nodes with a representitive load that is nominally the same as the output. By all means give it a go for a headphone amp, but for a 100W amp I would definitely think again.

If you need it clarifying further let me know.

Good luck!

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  • \$\begingroup\$ Do note that Q1 and Q2 are not output transistors, but input ones. These constitute the business end of a current-input amplifier. \$\endgroup\$ – Edgar Brown Dec 10 '18 at 2:54

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