I am trying to debug my VHDL project in Vivado 2014.03 on a KC705.
My project consists of multiple VHDL modules implemented as custom IP cores, which are connected in a block design.
mark debug on the signals that are connected to the ILA core.
After synthesis I used
setup debug and added the nets that my ILA core is analyzing. The .xdc file was modified and I even resynthesized the project just incase...
After writing the resultant binary file onto the FPGA, I get two ILA cores, both of which get stuck at "waiting for trigger". Sometimes my ILA cores responded to
trigger immediate, but they always return the same result and it isn't useful because the time window that I need is quite short.
I mapped one of the signals to an LED and confirmed that the signal exists.
I also synthesized the entire project in pure VHDL without using any custom IP cores. Again - I had the same problems.
I would like to make smart moves while debugging this issue, because each synthesis takes about two hours and it is very easy to make the project go out of date.
What could I be doing wrong? What can I try next?