7
\$\begingroup\$

I have an SMPS design that has the following properties:

  • 9-15V input voltage
  • 5V, 3A output
  • Switching frequency is 350kHz.
  • Switching controller is a LM25085.
  • The diode used is a DSSK48-003BS.
  • The switch is a FDS4953.
  • It's schematic is as follows (will be bigger if you click, opening in new tab recommended):

Here is the top copper layout. In this layout, bottom copper is a ground fill:

enter image description here

I know that increasing the copper area on the switch node will give me more EMI since it will be a bigger antenna then. Also, I know that breaking a ground plane will make the return loops follow a way rather than "right under the trace" which will yield in an increase in the loop area which will more open the doors to EMI, in addition to that, it can cause a ground bounce if the ground return has high \$\dfrac{dI}{dt}\$, like the return from the diode back to the input capacitor's ground.

With those in mind, if I create a cutout in the ground plane right under the pad of D1's cathode, which is the 2nd pin with a big SW on it on the bottom right of the PCB, and fill that cutout in the bottom layer with copper that is connected to the cathode of D1 with lots of thermal vias to create a heatsink, what are the advantages and disadvantages?

Also, can you critique my SMPS design?

Edit:

My PCBs arrived and it seems like I have connected my MOSFET wrong. I have exchanged drain and source connections, so it didn't work. Dead-bugged the MOSFET and soldered again. It doesn't work after 150mA at Vin=12V and after 130mA at Vin=10V. I have checked the MOSFET is working and changed the controller IC just in case, but no luck. Hope I will solve the problem..

More Edit:

The problem was my dummy programmable dummy load. It couldn't measure the voltage correctly and its min. input voltage was set to 5V. I set the minimum input voltage to 3V and the design is working very good now.

\$\endgroup\$
  • \$\begingroup\$ Before you people tell me that your MOSFET is overkill etc., I have to say that these are the only suitable ones with stock we can get from distributors in Turkey. Yeah, ask me about it, electronics design is hard in Turkey. \$\endgroup\$ – abdullah kahraman May 18 '12 at 5:09
  • \$\begingroup\$ Critique: Very tidy layout, though may cause slight complications in assembly due to low components being shaded by tall ones. \$\endgroup\$ – Jason Morgan May 18 '12 at 6:38
  • \$\begingroup\$ Cirtique2: I would be a little worried by the closeness of the gate of the fet and the copper fill on the switch input, noise might couple here causing very odd feedback issues. \$\endgroup\$ – Jason Morgan May 18 '12 at 6:46
  • \$\begingroup\$ @JasonMorgan Thank you. I will be assembling those by hand, so no problem. There is going to be only 50 of them. \$\endgroup\$ – abdullah kahraman May 18 '12 at 6:46
  • \$\begingroup\$ @JasonMorgan they are already close by the nature of the SO-8 package aren't they? \$\endgroup\$ – abdullah kahraman May 18 '12 at 6:47
7
\$\begingroup\$

First comments:

  1. Add a fuse. If the input polarity is accidentally reversed, your small diode near the input will clamp the input and burn.

  2. It's not a good idea to tie your switch gates directly together when PWM driven, as the gate capacitances can interact with each other. For reasonably-low frequency power supply designs, this can be fixed with a small series resistor (10 ohms) close to each gate. Microsemi has an app note on parasitic gate oscillation that explains the issue quite well.

  3. Ceramic capacitors should be derated 60-70% for voltage. (i.e. don't use 16V caps on a 12V output - use 25V). Also bear in mind that the dielectric material is important - X7R / X5R capacitors lose as much at 50% of their rated capacitance as their DC bias approaches the part rating. C0G and U2J dielectrics are largely immune from this. Kemet has an app note that mentions this (and other) gotchas with MLCCs.

  4. The bottom of the IC (in MSOP, which is what your PCB appears to be using) has an exposed pad which should be connected to a large ground plane for thermal dissipation. This device doesn't have integrated MOSFETs, but the MOSFET drivers themselves dissipate power and need to be cooled. If you're not using the part with the exposed pad, you should be! It's always better to have more cooling than you may need. Since you're driving two MOSFETs, the driver will be doing a fair bit of work. (On your schematic, the exposed pad is a no-connect - it should be going to your bottom-side ground pour with vias at the pad).

  5. From an EMI perspective, you've already done the most important thing of keeping your control circuitry away from your power paths. An isolated island for diode cooling shouldn't do bad things, since I don't see it appreciably changing any loop dimensions. A hard-switched buck is going to generate EMI no matter what you do, and your diode is going to be lossy. (If cost isn't a huge issue, the gains you get from a synchronous buck in terms of power loss in the lower switch vs. a diode are worth the extra investment.)

  6. Make sure that your overcurrent shutdown limit is below the 4.1A maximum DC current that your output inductor can handle. I didn't reverse any of your calculations to figure this out myself - too tired this morning :)

  7. You really should have some sort of output overvoltage protection. Ideally you want an SCR crowbar, in case you have a series MOSFET failure. The SCR clamps the DC input and blows the fuse (which you need to add per #1) while preventing your downstream components from all blowing up / catching fire due to receiving 9-15V instead of 5V. Also it protects you if your feedback goes open-loop (missing or bad part, bad soldering, etc.)

\$\endgroup\$
  • \$\begingroup\$ Hey, don't forget me! \$\endgroup\$ – abdullah kahraman May 19 '12 at 17:02
  • 2
    \$\begingroup\$ You really can't overestimate the importance of #2. In many designs where switching losses are significant and often dominate over conduction or diode losses, you will find a huge difference in device heating between the two switches without separate resistors to ensure they are in the plateau region of the switch simultaneously. I've experienced this myself in high-speed switch-mode designs. Let me know if you need a more thorough explanation of why this is important. \$\endgroup\$ – Nathan Wiebe May 20 '12 at 4:54
  • \$\begingroup\$ Also, why is C4 (1uF) so big and C1/2/3 (10uF) so small (are they 0805s? - can you even get 10uF 25V this small?)? Keep in mind that there will be a high ripple current on these caps and they better be able to handle the abuse that goes with being on the input of a buck converter. \$\endgroup\$ – Nathan Wiebe May 20 '12 at 5:06
  • 1
    \$\begingroup\$ @abdullahkahraman Break the connection between the FETs and to the control IC. Add a few ohms in series (up to 10; lower is better) between the IC and each FET. Scope the gate-source to make sure that the turn-on and turn-off are acceptably fast and without any excessive ringing. \$\endgroup\$ – Adam Lawrence May 22 '12 at 13:15
  • 1
    \$\begingroup\$ Coming back to this question after 6 years, after a little more experience in electronics, I understand that I cannot thank you enough for this answer.. It is pure gold.. Again, thank you very much! \$\endgroup\$ – abdullah kahraman Dec 14 '18 at 7:04
5
\$\begingroup\$

(I apologize for a second answer, but the asker asked for an elaboration on a comment that wouldn't fit in a comment)

With regards to using multiple switches in parallel without separate gate-drive resistors: When you start driving current into a MOSFET gate, if behaves like a capacitor and the voltage rises steadily. At a certain point (the plateau region), the voltage stops rising temporarily and the switch actually goes from not conducting to conducting. During this time, the switching node's voltage swings from 0 to Vin, and the gate-drive current goes to charging the miller capacitance. This is the region where the majority of the switching losses are incurred, as you briefly have voltage and current simultaneously. After the plateau, the MOSFET is on, the switching node voltage has reached Vin, and the gate-source voltage continues rising and approaches the voltage you are driving it with.

With 2 MOSFETs' gates locked together, you are forcing them to have the same instantaneous gate voltage. As no 2 MOSFETs are the same (manufacturing AND precise layout geometry differences), their threshold/plateau voltages will never be precisely the same. As a result, MOSFET A will hit its plateau first and the experience the whole switching loss of the circuit, while MOSFET B sits there not conducting anything because it is still off. Then after MOSFET A's plateau is over, MOSFET B hits its theshold voltage and turns on very quickly as it no longer has any drain-source voltage to switch. So basically only one MOSFET is switching under voltage, and incurs pretty much 100% of the switching loss.

The easy solution is to put small resistors between your gate driver and each MOSFET (like 10 ohm range). This way MOSFET A may start its plateau first, but MOSFET B's gate voltage will continue rising and soon it will be contributing to the switch in terms of discharging the parasitic capacitance of your switching node. I personally learned this the hard way through a product that was well within its thermal limits in our lab, but somehow had mysterious failures in the field. This was the issue.

\$\endgroup\$
2
\$\begingroup\$

Obviously only testing your exact layout would tell you for sure, but I don't think beefing up your switched node for conduction is necessary.  I would leave the ground plane under that region for EMI reasons (the switching node to ground capacitance will act as a natural snubber).  Also, assuming 1 oz copper, you shouldn't be hurting for current capacity on that already huge/short trace.  And lastly, the stitched plane could add heatsinking to your diode or inductor, but not your switch.  I would, on the other hand, watch the temperature on your switches and consider adding vias and bottom layer plane for heat dissipation to the left side of your switches.

Also, take special note of madmanguruman's #2 suggestion.

\$\endgroup\$
  • \$\begingroup\$ If I add a bottom layer plane for heat dissipation to the left side of the switches (on the net labeled sense), I will break the ground plane again. Won't that affect EMI? \$\endgroup\$ – abdullah kahraman May 20 '12 at 7:36
  • \$\begingroup\$ @abdullahkahraman Yes, and it's always a balancing act between EMI constraints and performance (and cost, and simplicity, and...). I only mention this as an option if your switch has heating problems. \$\endgroup\$ – Nathan Wiebe May 20 '12 at 13:44
2
\$\begingroup\$

You have already gotten some good answers so I'll only add one issue others haven't brought up.

I would try to keep the immediate currents in the loop of inductor - diode - cap off the main ground plane. That current is substantial and with high frequency components. I would also like to include the input cap in front of the switch for this too. Wire all these parts together in a tight loop, then connect the ground node of that loop to the main ground such that the loop current doesn't cross the ground plane. Only the net in or out current should go thru the connection to the ground plane. This minimizes the current on the ground plane, which keeps its voltage more constant. When high frequency current runs accross the ground plane, you have a center fed patch antenna.

\$\endgroup\$
  • \$\begingroup\$ This is a really interesting technique that I have never seen in the app notes or datasheets. I can create this easily in this design by just pouring copper right only under the high \$\dfrac{dI}{dt}\$ parts that you have noted, right? \$\endgroup\$ – abdullah kahraman May 21 '12 at 7:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.