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I have interfaced Xilinx 7 Series FPGA with TI processor- Sitara AM4376 over USB2.0.

I have implemented USB PHY through Cypress USB Controller IC - CY7C68014A (EZUSB-FX2LP). The attached file is the architecture I have implement for USB PHY between processor and FPGA. I can establish the data transfer from processor to FPGA from D+/D- to parallel data.

I am confused with how shall I send the data from FPGA to processor back, over USB when a respective request command is received by FPGA from processor. I have used processor in USB host mode and FPGA as a slave device mode.

Can some one help with this.

Thanks in advance.


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  • \$\begingroup\$ You're gonna have to be a bit more specific...the Cypress chip has a full 8051 processor inside; what is going on inside of that? \$\endgroup\$ – alex.forencich Aug 3 '17 at 2:40
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So you said you can transfer data from USB host to FPGA through CY7C68014A bridge. Therefore your host must be using packet transactions of OUT type.

To get the data in opposite direction, USB uses IN transaction. Host sends "IN" packet, and device sends the data back if ready, or NAK when data not ready.

But I am really curious how did you manage to construct OUT transactions if you don't know what the IN is for.

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