10
\$\begingroup\$

I am analysing some verilog code and found something like

wire z = |a & b;

while simultation the code behaves just like

wire z = a & b;

so i was wondering what is the meaning of the | (pipe) symbol? Does it have any impact on the simulation/synthesis?

\$\endgroup\$
17
\$\begingroup\$

This is a bit-wise reduction operator. |a & b means you apply a logical OR to all bits of a (producing a single bit) and then do a logical AND of that bit and b. |a has no effect when a is a single bit.

Nevertheless, it's quite common to see bit-wise reduction applied to single bit values. One typical case is auto-generated code where the actual width of a may depend on the configuration. Another possibility is this being legacy code where a once had several bits. When a became a single bit value, this line was still technically correct so the now unneeded reduction operator was left in.

| improve this answer | |
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.