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I need to design a TX/RX pair which functions like a HDMI 1.4 3D, for a proprietary HUD. The source signals are 2 distinct TFT output in RGB, and the sinks are also two separate OLEDs, and a stereo audio also need to be transferred in the same cable, but is on a lower priority.

The purpose is to reduce pin count of the cable connector.

LVDS signals on Xilinx spartan 6 could be transferred in meaning as GTP(PCIe) or SelectIO(TM) through IOB. The bandwidth estimation is about 600Mb/s in XVGA(single line).

Should i build a SerDes to bundle DVI(HDMI)signal in PCIe, or build something from scratch.

Thanks for your reading and your comment is valuable.

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  • \$\begingroup\$ I don't know if this is the proper place to ask it. \$\endgroup\$ – ShinTakezou May 15 '12 at 19:28
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    \$\begingroup\$ What format video are you starting with? If it is already in the FPGA, then you can just stream it out of the GTP - Xilinx's Aurora core is ideal for this. You can then aggregate other data with your video and stream it down the same pair. You do need a pair in each direction, or some handshaking signals between the two ends. And you'll need another FPGA to de-mux the data from the Aurora stream at the far end. \$\endgroup\$ – Martin Thompson May 18 '12 at 12:04
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    \$\begingroup\$ It would be helpful to know a little more about your architecture. Are you planning on having an FPGA on the sink/OLED side of the cable? What data format does the OLED require? Why HDMI 1.4 3d? HDMI is a display format though it can be used to transfer video between FPGAs. HDMI or even just DVI transceivers can be used to take 24 or 36 bits of parallel data and serialize it over 4 TMDS pairs. \$\endgroup\$ – davidd May 18 '12 at 15:15
  • \$\begingroup\$ @Martin thanks for the tip, aggregation and de-aggregation is very handy if available, could it be reasonable to aggregate RGB4:4:4 output from SOC with some meta data then decode at the sink, all by Aurora? \$\endgroup\$ – einzeln00 May 18 '12 at 17:23
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    \$\begingroup\$ As long as you do not violate certain timing and clock conditions (minimum clock, de/hsync/vsync transitions) you can put whatever resolution need over a set of HDMI/DVI link you control both ends of. \$\endgroup\$ – davidd May 20 '12 at 17:54
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Like Martin said, an Aurora implementation is eminently doable. It can also be done with a single differential pair vs 4 pairs for a dvi implementation. The clocking requirements for gtp transceivers can be pretty strict and the synchronization of the video can pose some challenges so make sure you understand ug386 and any other applicable Xilinx user guides.

A hdmi transmitter->receiver pair will work for you and might be simpler than a transceiver based solution. Hdmi is just dvi with some extras that you do not Ned added on, generally hdmi transmitters and receivers are backward compatible with dvi. Both are based on TMDS serial links, 3 data and 1 clock (4 differential pairs). When you control both ends of the link as long as you meet the basic requirements of the dvi standards for the (de,hsync,vsync) timing signals you can send any resolution you need. It does not need to be a standard video resolution.

Another potential solution is to use cameralink using the iserdes and oserdes blocks in spartan 6.

With any solution you will have to make sure the cable and board designs have have the needed signal integrity characteristics.

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Aggregating RGB 4:4:4 video with other data down Aurora is eminently doable. You'll need to multiplex the data yourself - come up with a simple wrapper which has a header stating the data type and length, and then packetise it yourself. I'd also recommend putting a very simple checksum or CRC on the end of each packet. This is not a rigorous "proper comms" type error detector, but it's a good way of catching the gross "oops, my fault" kind of errors in your HDL code, or in parsing software. Things like FIFOs being read whilst empty, bytes being dropped, frame lengths being reported wrong etc.

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