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This is a description of LDO in Switch-Mode Power Supplies Spice Simulations and Practical Designs by Christophe Basso.

I am wondering if there is any mistake here. The author said that for linear regulator using NPN pass transistor, Vin shall be above Vout by a Vbe, at least. I don't understand why. I think it may meant to say the base voltage should be about Vbe above Vout instead. Can someone explain?

Figure 1-2 finally shows how our resistive converter could be improved, let’s say for the 5 V section. The error amplifier is made via a voltage-controlled voltage source (E primitive) and features a gain of 10k (or 80 dB). One of its input receives the voltage reference whereas the other one, the inverting input, is biased by a portion of the output voltage. This is actually a linear regulator, however, limited in the input voltage range since Vin shall be above Vout by a Vbe, at least, to guarantee a proper drive for Q1. If Vout is below the target (5 V in our example), E1 output increases and strengthens Q1 bias current: Vout goes up. On the other hand, suppose the load has suddenly been reduced, therefore Vout exceeds 5 V. Thanks to E1, Q1 bias current goes down, reducing the output voltage until regulation is met again.

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    \$\begingroup\$ Correct, the base voltage should be. But how do you power your error amp? It must be able to drive to a voltage Vbe above Vout which means it needs a supply of at least Vbe above Vout, hence Vin must be so. \$\endgroup\$ – Tom Carpenter Aug 2 '17 at 22:10
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You are absolutely correct that Vbase should be above Vout by Vbe.

I believe the author's point is that Vbase is supplied by the error amplifier, and that the error amplifier is powered by Vin, therefore Vin has to be at least as high as Vbase (Vout + Vbe) in order for the circuit to work.

I have just started reading this book myself, and can't help noting a distinct lack of rigour in its treatment of the subjects I've looked at - such as, making this point explicit. I still think it's a useful book as long as I treat it as guidance rather than as an authoritative reference.

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The explanation is correct for the schematic given , however if a PNP or Pch FET were used this drop can be reduced. typical Bipolar LDO's need 1 to 2.5V drop due to the NPN output and bias voltage above output dependent on load current.

Whereas Pch LDO's can have dropout V in xx mV range depending on If* Rdson

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  • \$\begingroup\$ I believe TI, and likely others too, have some LDOs featuring internal charge pumps to supply the error amplifier. Given the amount good PSRR of a differential amplifier this doesn't influence the output nouse performance but also allows for much lower drop. Don't know what they use for a series pass element though. \$\endgroup\$ – Joren Vaes Aug 3 '17 at 5:33

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