This is a description of LDO in Switch-Mode Power Supplies Spice Simulations and Practical Designs by Christophe Basso.
I am wondering if there is any mistake here. The author said that for linear regulator using NPN pass transistor, Vin shall be above Vout by a Vbe, at least. I don't understand why. I think it may meant to say the base voltage should be about Vbe above Vout instead. Can someone explain?
Figure 1-2 finally shows how our resistive converter could be improved, let’s say for the 5 V section. The error amplifier is made via a voltage-controlled voltage source (E primitive) and features a gain of 10k (or 80 dB). One of its input receives the voltage reference whereas the other one, the inverting input, is biased by a portion of the output voltage. This is actually a linear regulator, however, limited in the input voltage range since Vin shall be above Vout by a Vbe, at least, to guarantee a proper drive for Q1. If Vout is below the target (5 V in our example), E1 output increases and strengthens Q1 bias current: Vout goes up. On the other hand, suppose the load has suddenly been reduced, therefore Vout exceeds 5 V. Thanks to E1, Q1 bias current goes down, reducing the output voltage until regulation is met again.