# Small Slope On Square Wave Generator Output

I have made a square wave generator using 555, however there is a small slope on the high level of the square wave as you can see below. How can i overcome and obtain a straight high level of signal? My aim was getting 16 kHz frequency and %50 duty cycle and measurement is so close to this values. My only problem is that small slope. Thank you so much.

This is my circuit;

This is my measurement:

• Your schematic is a mess, why is C2 at top left when it is only connected to the bottom right pin ? Avoid wire crossings and corners as much as possible. My brain hurts when trying to see what you made. Google "555 circuit" for examples how to draw a more readable circuit. – Bimpelrekkie Aug 3 '17 at 11:46
• You are right i have done this at 3 am, this was the reason. – layout789 Aug 3 '17 at 11:47
• My guess is that the slope of the "high" output voltage is caused by the voltage drop of the output pin. The charge current (for charging C1) decreases over time and so does that voltage drop. But if you feed this signal to a standard CMOS (inverter) gate the slope will be gone. – Bimpelrekkie Aug 3 '17 at 11:49

## 2 Answers

1. Try adding a second capacitor between VCC and GND to further stabilize the supply, 100µF should do
2. Add a low-pass filter to the output thats not deforming your signal too much but filters out that annoying peak. 100nF and ~50Ohms should do the trick and not deform your signal too much. If it rounds your squarewaves corners too much you can try to use a smaller cap (22nF) or smaller resistor.
• It worked. So small a vibration happens only. This is the image of non-slope signal: imgur.com/a/8OFTY – layout789 Aug 3 '17 at 12:29
• You can always tweak the filter a little if you want it to perform better, just increase one of the values to smooth it more. But looks decent already, glad I could help. – Alexander Krämer Aug 3 '17 at 12:31
• I have removed the filter and put on and it decreased. Before it the vibrating is on the video as you can see youtube.com/watch?v=0phwAsMgOwk&feature=youtu.be – layout789 Aug 3 '17 at 12:38
• Do you mean the inconsistent duty cycle? That's normal, for one the 555 is not a perfect chip, also the oscilloscope isnt perfect at measuring. The important thing is that the duty cycle is always around 50% +/- 0,5% or so, as long as your frequency is stable this shouldnt matter too much. Of course it depends on what you want to use the circuit for. – Alexander Krämer Aug 3 '17 at 12:43

Did you not consult the datasheet?

The method above uses $R_A=R_B$ for 50% duty cycle with complementary BJT outputs that exhibit two diode drops from Vcc to Voh and Vce(sat) for Vol. You add a 1~10k pull-up $R_L$ to 5V rail to overcome the high side limitations for being near the low supply voltage. (4.5Vmin)

A far more ideal clock can be made with any Schmitt Trigger CMOS gate with R feedback and C input to gnd. 74xx14 model.

(Also) Please draw your schematics like the datasheet from left to right and no scattered lines. You drew the physical layout instead of a "logical" layout. This is why we also call them "Logic Diagrams", and not "physical" schematics. We assume you know physical orientation.

• There is no combination of Ra and Rb which will give you a true 50% duty cycle with that circuit. Ra = Rb gives 66.6%. Even a 100:1 ratio still gives a little over 50%. – brhans Aug 3 '17 at 16:58
• This is why I never use 555's get a 'HC14, except you are connected to output Pin3 rather than Pin2,6 for Rb or better yet run at 2x then use a D FF divide by 2 – Sunnyskyguy EE75 Aug 3 '17 at 18:58