# SPI Bus Routing: Signal Integrity Issue?

I am routing a two-layer PCB with a 10MHz SPI bus. (See picture below.) The device on the left is the 5V master, the device on the right is the 3.3V slave, and the IC in the middle is a 74XX08 quad AND gate to perform level conversion on the MISO line.

The trace labeled SO is the slave's MISO which goes to pins 1 and 2 of the 74XX08. This is converted to 5V and output on the 74XX08's pin 3 which goes to the master on the trace labeled RX1.

The master's MOSI line goes directly to the slave on the trace labeled TX1 (bottom layer).

Finally, the master's SCK line goes directly to the slave on the trace labeled XCK1.

All of the other traces in the vicinity are extremely low speed.

My main concern is that the SCK, MOSI, and MISO lines cross over each other near the bottom right of the picture. Will this, or other aspects of the design be a problem at 10MHz?

RX1 length: 15.275mm

TX1 length: 17.834mm

XCK1 length: 23.700mm

SO length: 6.706mm

• Your greatest concern at 10MHz should be the ground layout. Do your currents take the shortest way back to the source (the chip with the push transistor) possible? – Janka Aug 4 '17 at 0:40
• What is the "XX" in your 74XX08? The technology of that part may be significant. – Peter Bennett Aug 4 '17 at 0:58
• @PeterBennett The XX stands for LS or HC or HCT. As long as the particular part is compatible with the voltages and switching speeds, I would not think it's much of an issue. They are all pin-to-pin compatible. – HaLailah HaZeh Aug 4 '17 at 1:01
• LS and HCT have lower input High threshold voltages than HC - it may or may not make a difference in this case, but you should specify the particular type you are using. The several varieties of 74XX TTL-ish parts may all be pin-compatible, but are not necessarily fully interchangeable. – Peter Bennett Aug 4 '17 at 1:04
• @PeterBennet Actually, I will probably use the 74ACT08. Input high level = 2V, max switching time = 10ns. – HaLailah HaZeh Aug 4 '17 at 1:13

## 3 Answers

Well, the XCK1 trace crosses over the other two horizontal traces in the vertical direction. That is definitely positive and something that you would want to do if you can't avoid that signals cross each other. The reason is that in this way you can minimize crosstalk effects between these traces.

On the contrary, there is a small part at the bottom left corner of the image where RX1 and TX1 are routed one being directly above the other. I mean, for such a short distance this probably won't be any real problem. But to be sure you should probably try to move one of the two. Perhaps route TX1 between pins 12 and 13.

• Thanks! I actually routed RX1 between pins 12 and 13 since it was a little easier. – HaLailah HaZeh Aug 5 '17 at 1:41

Your traces are reasonably short and your SPI signals are all actively driven (not open-collector, floating, or passive pull-up). So in that regard I don't anticipate a problem.

Magnetic fields may be a problem.

Consider 200pF load on any SPI line. Assume 5 volts in 10 nanoseconds. Using $$I = C * dV/dT$$, the line-charging current is 200pF * 0.5v/nanoSec or 100 milliAmps.

That current must rise in less than half the total edge rate, perhaps in a triangular waveform, to a peak of 200 milliAmps in 5 nanoSeconds.

If you have 15mm by 2mm loop, located 1.5mm from the 200mA current, the induced (magnetically induced) voltage is

$$2e-7 * Area/Distance * dI/dT$$

2e-7 * 15mm * 2mm / 1.5mm * [1meter/1000mm] * 40mA/nanosecond

Vinduce = 2e-7 * 20mm/1000mm * 0.04amp/1e-9

Vinduce = 2e-7 * 1e-3 * 20 * 0.04 * 1e+9 = 1.6 e-1 = 0.16 volts of noise

• Are you basically saying that the noise is insignificant? – HaLailah HaZeh Aug 4 '17 at 19:22