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Im building a homebrew 8 bit computer and having some problems with video output.

I want to know if its possible to generate high resolution, say 640x480, monochrome video output, PAL or NTSC, using a microcontroller, say atmega328 running at 20MHz, a 8 bit PISO shift register and a DRAM external framebuffer, address bus can be controlled by another SIPO shift register.

Can I generate an 640x480 monochrome output with an atmega? Is there a better way?

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  • \$\begingroup\$ I've never heard of anyone interfacing an AVR with a DRAM... I could be wrong, but that sounds like a job for an FPGA to me. That being said, it's definitely possible to generate NTSC signals with an AVE, but you probably have to write assembly to get the timing tight enough. \$\endgroup\$ – vicatcu Aug 4 '17 at 2:04
  • \$\begingroup\$ This is similar to what you want to do: lucidscience.com/pro-vga%20video%20generator-1.aspx \$\endgroup\$ – HaLailah HaZeh Aug 4 '17 at 2:06
  • \$\begingroup\$ @vicatcu Yeah, i was thinking about FPGA (or even CPLD) but they are quite expensive here. It would help alot any alternative. I dont have much problem with AVR assembly, but most projects works only with low resolutions due to speed issues. \$\endgroup\$ – h0m3 Aug 4 '17 at 2:06
  • \$\begingroup\$ The Uzebox uses an ATmega644 overclocked to 28MHz to generate up to 720 pixels per line purely in software. \$\endgroup\$ – Janka Aug 4 '17 at 2:16
  • \$\begingroup\$ @Janka This project is really interesting and may help me alot! The atmega644 is easy to find. \$\endgroup\$ – h0m3 Aug 4 '17 at 2:19
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In NTSC, the active portion of a horizontal line is 52.6 us. To pack 640 pixels in there would take a 12.17 MHz shift clock and a 1.52 MHz load rate. I don't think an AVR can generate a read address, read the data, push it out to the PISO shift register, and calculate the next RAM address fast enough.

Going back in time to microprocessor-based video terminals, they used the micro's for the user interface and writing to the (dual-port) video RAM. Scanning the RAM and turning its contents into video was all random hardware. Today that hardware certainly would fit in one CPLD or FPGA, but functionally it still would be a non-firmware engine.

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  • \$\begingroup\$ Yeah. You're right. Im avoiding CPLD or FPGA because of the price actually, they are very expensive here. I was thinking. If i store the ASCII on AVR flash and emulate a VT100 instead of use an external framebuffer, it would be much faster to gather the data and feed the shift register (theres some calculations, but reading from internal flash shoud be faster). I was doing some math and if Im not wrong, theres ~104 cycles between a shift load and another (using a 8 bit shift register). Something close to 50 instructions in AVR architecture. \$\endgroup\$ – h0m3 Aug 4 '17 at 5:36
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Datapoint Corporation, which defined the Intel 4004 architecture (which Intel balked at building), used all PMOS shift registers in its early terminals. The founders (originally at Computer Terminal Corporation) were Phil Ray and Gus Roach, who refined their computer understanding being program managers for NASA ground terminal equipment for Gemini telemetry equipment. In defining their "terminals", they included fully programmability, knowing they were really selling computers. With all memory being Shift Registers.

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    \$\begingroup\$ analogsystemsrf - Excellent bit of history. \$\endgroup\$ – AnalogKid Aug 12 '17 at 16:06

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