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I've done a lot of googling and the answer just isn't jumping out at me.

I've got a project that has two SD card slots. Access to the two cards is never simultaneous. I'm upgrading this project to an ATSAMS70N19 (mainly to get hi-speed USB), which has an HSMCI interface... but only a single one.

How can I multiplex the two card slots across this interface?

I already know that I can properly multiplex two cards in SPI mode using the !CS line (my current version of the project does that), but I am hoping to increase performance with the HSMCI interface.

I'd like to use a GPIO pin as an A/!B pin. The spec that I'm reading at least seems to suggest that I can simply switch the clock back and forth between the two cards (holding the idle card's clock either high or low) is enough to keep the idle card out of the way. Is this correct?

If this isn't good enough, how can I switch the whole bus back and forth between the two slots given that 5 out of the 6 pins are bidirectional and relatively high speed?

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  • \$\begingroup\$ You could probably gate the clock, but you'll need to be very careful about the timing relationships between the signals. You may have to find a gate with a very low propagation delay for that to work, and you may run in to issues with pushing the clock as fast as possible. Another option to consider might be using a pair of bidirectional bus switches, and delaying all of the signals by the same amount. \$\endgroup\$ – alex.forencich Aug 5 '17 at 4:30
  • \$\begingroup\$ What speed of SD bus you are planning to use? \$\endgroup\$ – Ale..chenski Aug 5 '17 at 6:19
  • \$\begingroup\$ And how long is your SD bus? \$\endgroup\$ – Ale..chenski Aug 5 '17 at 6:58
  • \$\begingroup\$ The entire device is 4 square inches, so the bus will be quite short. I am aiming for a 25 MHz speed. @alex.forencich, can you give me a pointer to a bidirectional bus switch? I couldn't find such a thing, and if I wanted to mux the entire bus, it sounds like the right tool for the job. \$\endgroup\$ – nsayer Aug 5 '17 at 13:13
  • \$\begingroup\$ @alex.forencich Might the QS3VH257PAG8 be something along the lines you're thinking of? Using your description for it in google brought me a whole new series of search results, and this looks kinda promising. \$\endgroup\$ – nsayer Aug 5 '17 at 13:32
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You could probably gate the clock, but you'll need to be very careful about the timing relationships between the signals. You may have to find a gate with a very low propagation delay for that to work, and you may run in to issues with pushing the clock as fast as possible.

Another option to consider might be using a pair of bidirectional bus switches, and delaying all of the signals by the same amount. This might actually be your best bet. Several companies make fast FET based bidirectional bus switches that can pass high speed signals with low propagation delays. One 8 channel switch for each socket would be perfect. The switches are usually 5v tolerant, don't have ESD protection diodes to Vdd, and they clamp passed signals at Vdd, so they can be used for fast level translation.

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  • \$\begingroup\$ I once gated the clock and my teacher went berserk on me. \$\endgroup\$ – Harry Svensson Aug 5 '17 at 16:04
  • \$\begingroup\$ @HarrySvensson, your should differentiate between clock gating in some low-level piece of self-contained RTL from a carefully managed clock control. Properly managed clock "gating" is everywhere today to save power, enabling-disabling clock trees is common. \$\endgroup\$ – Ale..chenski Aug 5 '17 at 17:51
  • \$\begingroup\$ @AliChen Yeah I did that to save power and minimize the amount of logic needed, according to my teacher he did not find it justified... but it's assuring to know that it's actually happening. Thanks for sharing that information. \$\endgroup\$ – Harry Svensson Aug 5 '17 at 17:55
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    \$\begingroup\$ Clock gating is extremely common on ASICs. The timing analysis can ensure that it will work correctly. However, clock gating on FPGAs is much more difficult to implement reliably due to the clock network not really being designed to be gated, and the difficulty of doing timing analysis from logic sourced clocks. \$\endgroup\$ – alex.forencich Aug 6 '17 at 0:45

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