Confused on MOSFET terms (velocity limited, mobility limited, constant mobility)

So we're learning about transistors, but we don't much of the physics behind how they work (yet) so these terms are quite strange to me. The models we've used are "velocity limited", "mobility limited", and "constant mobility". In some models, the relation between drain current and gate-source voltage is linear and in others it's based on a square law. What do these terms mean, and where do the square or linear relationships come from?

Here's the equation for velocity-limited characteristics: $I_d=V_{sat} C_{ox} W_g (V_{gs}-V_t) (1+\lambda V_{ds})$

And this is for mobility limited (which they also refer to as constant mobility): $I_d=\frac{1}{2} \mu C_{ox} \frac{W_g}{L_g} (V_{gs}-V_t)^2 (1+\lambda V_{ds})$

There are various modes of operation in MOSFET transistor. The standard modes are: cut-off, linear and saturation. The FET transitions between these modes in accordance to applied bias (bias = voltages).

The equations you posted refer to a single mode of operation - Saturation. It is fine, because FETs are indeed most commonly used in saturation, but you must keep in mind that the below explanations may not be relevant to other modes (cut-off and linear).

Note that the term $(1+\lambda V_{ds})$ is common to both equations, therefore it may be omitted for the sake of current discussion (in fact, this term, which represents Channel Length Modulation, is completely irrelevant to your question). Therefore, let us concentrate on two forms of MOSFET I-V characteristic equation for saturation region:

1) $$I_d=\frac{1}{2} \mu C_{ox} \frac{W_g}{L_g} (V_{gs}-V_t)^2$$

2) $$I_d=V_{sat} C_{ox} W_g (V_{gs}-V_t)$$

We must also recall the definition of current (amount of charge per unit time): $$I=\frac{Q}{t}$$

In light of this simple equation, we will be able to understand the differences between the above two equations if we can identify what is the charge and what is the time in each case.

The "usual" relation

The basic model of MOSFET (where gate is seen like a simple capacitor) states that: $$Q_{inv}\propto C_{ox}(V_{gs}-V_t)$$

The time it takes a charge carrier to transit from source to drain (distance divided by velocity) is: $$t=\frac{L}{v}=\frac{L}{\mu E}=\frac{L}{\mu \frac{V}{L}}\propto \frac{1}{\mu (V_{gs}-Vt)}$$

Take the above and substitute for $I$: $$I \propto \mu C_{ox}(V_{gs}-V_t)^2$$

You can see that under assumption of $v=\mu E$ we came to a quadratic dependence on Gate-to-Source bias.

There is one fine point here: why do I claim that the electric field which accelerates the carriers is related to $V_{gs}-V_t$? I won't get into explanations here, but this is true for saturation mode only.

Velocity saturation relation

Velocity saturation has no effect on the inversion charge, therefore: $$Q_{inv}\propto C_{ox}(V_{gs}-V_t)$$

However, when calculating the transition time we assume that the velocity of the charge saturates. In other words: the velocity does not increase for stronger electric fields and we must replace $\mu E$ with $v_{sat}$ (saturation velocity is assumed to be constant): $$t=\frac{L}{v}=\frac{L}{v_{sat}}$$

Take the above and substitute for $I$: $$I \propto v_{sat}C_{ox}(V_{gs}-V_t)$$

This time we observe a linear dependence on $V_{gs}$.

Summary

The only difference in assumptions which led to the discrepancy between these equations is that in the "usual" case we assume $v=\mu E$ (carrier's velocity is proportional to the electric field), whereas in "velocity saturated" case we assume that the velocity saturates at some constant value and will not increase in stronger electric fields (therefore the name "velocity saturated equation").

Hope this helps.

Although MOSFET are linear voltage control switches, the gate charge during transition means you have to dump current from the driver to the gate capacitance during transition. Since you know the square law of V for the Cap current, it is quadratic during transition and linear beyond that. My rule of thumb is assume 50:1 impedance ratio for driver on gate to load on drain or source. For faster transition times they use Diacs to dump a capacitor storage into the gate or low impedance MOSFETs to drive even lower power MOSFETs. eg 50mΩ drive to gate with 1mΩ output. 100:1 is also possible. Anything where Source does not match line and load will lead to skew, ringing from mismatched impedances from source to load.

The same holds true for high power IGBT's.