Verilog: Pass a vector as a port to a module

Question

I have two modules

1. counter: Output is a vector called error_count.
2. lcd: Module to display the code on an LCD. Input includes clock and error_count.

Following snippet of the code is most relevant and attached below:

1. Top level module:

   counter counter1 (..., error_count);
   lcd lcd1 (..., error_count);

2. counter module:

   module counter (..., error_count);
   ...
   output reg [31:0] error_count = 0;
   ... //Update counter every clock cycle
   endmodule
   

3. lcd module:

   module lcd (..., error_count);
   ...
   input [31:0] error_count;
   ... //error_count used to display on LCD
   endmodule
   

What is wrong with this code? The display just prints 0 as the output. Is there anything wrong with the way I am passing the the vector?

Additional Info: I am using the Xilinx Spartan 3E starter kit for testing this code. The LCD code is fine and I have tested it with local counter (which was reg[31:0]).

Answer 1

The code you showed has a few problems:

• You don't show how error_count is declared in the top-level module. If error_count is just declared as wire error_count;, you only have a single bit of your counter connected between the counter module and the lcd module.

• You don't show how the counter is updated in the counter module. You could have a bug there that results in the counter never updating. Since it is initialized to 0, you'd always have a 0 output from the counter module.

• You don't show any clock input to the counter module. If clock is not connected, error_counter will never be updated.

• You say that lcd has a clock input, but you don't show that it actually does, and you don't show any code where it matters.

• You don't show how your clock is generated. If there's no clock, the counter won't updated.

• You don't show the complete input and output ports to either module. With your coding style it's easy to connect a wrong input to a wrong port. I much prefer to intantiate modules with the syntax like

  counter counter1 ( .clk( clock ) , .error_count( error_count ) );

  With this style, the order of naming the in's and out's in the instantiation doesn't matter.

• You haven't shown any reset signal, but you probably have one. If the reset is stuck in the active state, probably the error_count won't ever increment.