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I'm working in a digital engineering lab and I'm trying to figure out how this debouncing circuit works. It's provided as-is by Xilinx but I'm not quite sure why it does what it does. Any pointers, perhaps? Following is the VHDL code:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity Debouncer is 
    Port ( CLK : in  STD_LOGIC; 

           Sig : in  STD_LOGIC; 
           Deb_Sig : out  STD_LOGIC); 
end Debouncer; 
architecture Behavioral of Debouncer is 
 signal Q0, Q1, Q2 : STD_LOGIC := '0'; 

begin 
process (CLK) is 
begin 
 if (CLK'event and CLK = '1') then  
  Q0 <= Sig; 

  Q1 <= Q0; 

  Q2 <= Q1; 

 end if; 

end process; 

Deb_Sig <= Q0 and Q1 and (not Q2);

end Behavioral; 
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  • \$\begingroup\$ What do you understand? \$\endgroup\$ – Kortuk May 20 '12 at 12:31
  • 1
    \$\begingroup\$ When trying to understand VHDL, it's always best to try to draw a diagram of what it's doing, either at the signal level or at the gate level, as Teleclavo shows below. For debouncing in general, it is important to know the characteristics of the incoming signal, which in turn determine the clock speed of an entity like this and the number of samples you ought to take. \$\endgroup\$ – Kevin H May 20 '12 at 21:04
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I'm not familiar with VHDL, but it seems to be doing this: output Deb_Sig is 1 only when input Sig has been 0->1->1 (time grows to the right), sampled at the rising edges of CLK. Otherwise, Deb_Sig is 0. So, the module detects rising edges at the input, and only those ones that are followed by a high level that, after sampling, turns into at least two logic 1 samples. That way, it will ignore pulses that are high during only one sampling instant, which will be considered noise.

I would say that your code synthesizes something equivalent to this:

Figure

Curiously enough, it may ignore high pulses that last 2T-epsilon (where T is the sampling period), and detect high pulses that last T+epsilon (which is shorter than 2T-epsilon), if the sampling is such that it sees only one logic 1 in the former pulse, but two logic 1s in the latter one.

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I believe, this debouncing circuit is for the active high input. It uses the three flip-flops. 1st flipflop accepts "sig" and output "Q0". 2nd flipflop accepts "Q0" and output "Q1". 3rd flipflop accepts "Q1" and output "Q2". This three flip flops implementation is to avoid/ignore any glitches at the input. It drives the output signal only if the input signal state (logic 0 or logic 1) is stable for atleast three clock cycles "3 x clk - rising edges".

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