The design block in question is generated by Quartus, it is the shift register megafunction. When I simulate the design I find that some of the signals do not show 0 or 1, rather they show different expression for value:
Where is says Pu0, these are connected to logic 0 permanently. Where it says St0, that is driven low and where it says St1 that is driven high, but not permanently. Why do I see this instead of 0 or 1?