I am trying to simulate a decade counter using a ripple counter 4 bits and a NAND gate to reset the 4 J-K flip-flops when it reaches 10 (1010). enter image description here

The thing is it does not reset but goes to 4 (0100) due to the reset on my second flip-flop (it sends a negative edge to the next one plotted on pink) as shown in the plot (the tiny line on the green plot). is this a failure on the simulation or in the design? Any suggestion to solve that will be appreciated

the software I am using is a livewire Ripple counter circuit on livewire

  • \$\begingroup\$ Are you willing to make it an actual digital system, or is the fiddling with gate delays part of the assignment? \$\endgroup\$
    – DonFusili
    Apr 10, 2019 at 9:14

2 Answers 2


The problem is as you say "The thing is it does not reset but goes to 4 (0100) due to the reset on my second flip-flop (it sends a negative edge to the next one)"

There are two alternative solutions to this problem:

1) Lengthen the reset pulse with a monostable.

2) Delay the reset pulse, but to IC1a only. This would then reset IC1a after the negative edge from the output of the second flip flop has passed. Might get a glitch on the output of IC1a though. A two inverter delay to the !clr pin of IC1a may be long enough.


Replace two input NAND gate with four input NAND gate ,connect flip flop outputs Q0 and Q2 directly to it. Pass Q1 and Q3 through NOT gate and then connect the outptut to input of 4 input NAND gate. Apply the output of 4 input NAND gate to the clear of four flip flops. See if it works.

  • \$\begingroup\$ I tried what you suggested, and there is no difference, thanks \$\endgroup\$ Aug 7, 2017 at 4:40
  • \$\begingroup\$ youtube.com/… \$\endgroup\$
    – Parth
    Aug 7, 2017 at 4:41
  • \$\begingroup\$ The reason for why it might not work as @user29344 is describing might be because the set value is wrong. Right now it appears to be floating. \$\endgroup\$ Aug 7, 2017 at 5:21
  • \$\begingroup\$ @HarrySvensson the set values are not floating (the value is not displayed because the simulation is paused), and I am starting to think that there is an exagerated delay on the propagation of the signal on the flip flops \$\endgroup\$ Aug 7, 2017 at 8:02
  • \$\begingroup\$ @E.VillalobosG. - Try adding a pair of NAND gates configured as inverters to the output of your existing NAND gate. In other words, delay your reset pulse a bit. What you are seeing is (essentially) a classic problem using a FF output to directly reset itself. \$\endgroup\$ Nov 8, 2018 at 12:41

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