The thing is it does not reset but goes to 4 (0100) due to the reset on my second flip-flop (it sends a negative edge to the next one plotted on pink) as shown in the plot (the tiny line on the green plot). is this a failure on the simulation or in the design? Any suggestion to solve that will be appreciated
Replace two input NAND gate with four input NAND gate ,connect flip flop outputs Q0 and Q2 directly to it. Pass Q1 and Q3 through NOT gate and then connect the outptut to input of 4 input NAND gate. Apply the output of 4 input NAND gate to the clear of four flip flops. See if it works.
The problem is as you say "The thing is it does not reset but goes to 4 (0100) due to the reset on my second flip-flop (it sends a negative edge to the next one)"
There are two alternative solutions to this problem:
1) Lengthen the reset pulse with a monostable.
2) Delay the reset pulse, but to IC1a only. This would then reset IC1a after the negative edge from the output of the second flip flop has passed. Might get a glitch on the output of IC1a though. A two inverter delay to the !clr pin of IC1a may be long enough.