# Synopsys Synthesis with underlying modules as gate libraries

I am trying to synthesize my Verilog modules into 1 top module which contains all the modules extracted into 1 top module.

With setting -hierarchy option in write_file, I get all the modules separately. I am not really sure if I explained it properly as I am quite new to this.

• Could you check your compile or compile_ultra command? There may be a switch that disables ungrouping. – ahmedus Aug 7 '17 at 14:24
• Thank you for your answer, simply replacing compile with compile_ultra did the trick. – Damian Aug 8 '17 at 7:12
• Many years since I used synopsys but if I recall correctly the command to remove the hierarchy was "ungroup -all -flatten". – Oldfart Dec 5 '17 at 19:59

The problem has been fixed by the compile_ultra command as mentioned in the comments. Here is some explanation.
If the compile command is used, ungrouping is disabled by default. So it should be enabled explicitly.
compile -ungroup_all

On the contrary, auto ungrouping is enabled by default if the compile_ultra command is used. No additional option is required in this case.
compile_ultra