# Passive Impedance Match Losses

I'm starting my first scratch design FM receiver. I pulled the S parameters from an RF amplifier datasheet and designed an input matching circuit. A new question popped up when I looked at the spice outputs:

The matching circuit is showing that the signal is maxed out around -11.6 dB. The amplifier has a gain of 26 dB. Does this mean that the effective gain will only be 14.4 dB? I know this is probably a very basic question but I can't seem to find any explanations that show gain of each stage including matching losses. Obviously a 12 dB lower output than expected is a pretty big difference. I don't want to over amplify and blow out the next component in the chain. • Do you in fact mean maxed out at -11.6 dBm? The "m" is extremely important. Aug 7, 2017 at 14:48
• Which node in your circuit is n002? The graph is meaningless without that information. And which components are representing your matching network and which ones represent the receiver? Aug 7, 2017 at 16:25
• I simulated the match circuit with an AC source of amplitude 1, therefore the output magnitude should be relative to whatever real input the circuit so no matter what input I get in the receiver, by the time it hits my amp I am asking if it really drops 11.6db. Vn002 is across the output resistor(R1, which in input resistance of the amp). R2 is source resistance. C3 is input capacitance pulled from the amp spec sheet. I'm only modeling input, no output. L1, C2, c3 are matching elements. Aug 7, 2017 at 16:57
• Note that LTSpice is plotting dBV (dB relative to 1 V), not dB (ratios of power). The power transfer will be somewhat better because 1 V across 33 ohms is more power than 1 V across 50 ohms. Aug 7, 2017 at 17:29

The matching circuit is showing that the signal is maxed out around -11.6 dB. The amplifier has a gain of 26 dB. Does this mean that the effective gain will only be 14.4 dB?

If the 32.69 ohms represents the input impedance into your amplifier then yes, the net gain will be only 14.4 dB.

I have to say that I'm a little confused about why you are using this matching circuit - maybe you have a long feed line from your signal source to the amplifier but, if you haven't, you might find a better solution with a pi netwoork of two capacitors and an inductor or two inductors and a capacitor. It's even feasible that a simple two resistor solution might give better than -12 dB.

If I use an online calculator that adopts the following circuit: - With 6 dB attenuation (best possible) and trying to match 50 ohms to 33 ohms I get: -

• shunt in = 2157 ohms
• shunt out = 56.6 ohms
• series = 30.3 ohms

There is also this one from Analogue devices that matches to a parallel complex load such as an R and a C: - And if there's any doubt about the ADI tool here are the plots of gain (blue) and input current (green): - There is an insertion loss of 1.8 dB and the input current at 100 MHz is 20 mA at a phase angle of 0 degrees. This corresponds to an input impedance of 50 ohm given that the input voltage is 1 volt.

• I've added a passive filter and link - if you want to "hide" or mask the input capacitance then a parallel inductor of the right value to resonate at 100 MHz would seem the only addition to the above circuit. BTW it seems a big input capacitance! Aug 7, 2017 at 17:27
• BTW you did say in your comment below your question that "L1, C2, c3 are matching elements". I take it that you meant C1 and not c3? Aug 7, 2017 at 17:31
• Yes. Corrected here: L1, C1, and C2 are a three element L filter are they not(as you suggest two caps and an inductor)? C3 is the input capacitance of the amp itself. Do you have another topology to suggest? I would like to minimize input loss as much as possible, I'm not sure what a typical passive match loss value is. I will try the pi network with a parallel inductor. Thanks for the tip Aug 7, 2017 at 17:40
• There is also the second calculator that should have less loss than the resistive one. Aug 7, 2017 at 17:58
• @JohnThompson Have you got this sorted out yet? Aug 10, 2017 at 9:33