In Vivado, implementation of my projects can take a while especially if I use debug cores. What can I do to make implementation faster? I tried the "RuntimeOptimized" constraint and it made no difference. Is there an option for less optimization and faster compilation? If I debug nets as "data" only and not "data and trigger" will it make it faster?

Often I am changing small things in order to debug my firmware. I feel like this is the wrong way to do it, but I'm not sure what else to do when I get results different from those I simulated (I use ActiveHDL to simulate).

Is there a way to reduce implementation time if I made only minor changes?

Is it possible to improve my VHDL code to make things faster?

Thanks for any help.

  • 2
    \$\begingroup\$ Debugging should mostly be done in simulation; the synthesis/P&R time in then relatively unimportant. \$\endgroup\$ – Brian Drummond Aug 7 '17 at 21:57
  • \$\begingroup\$ It isn't the analysis of the source code that consumes the bulk of the time. That part is relatively quick. It's the mapping of the abstract functionality described by the source code to the physical resources of the device that takes most of the time. The only way to speed it up significantly is to drastically reduce the functionality of the design, or to get a much faster machine. \$\endgroup\$ – Dave Tweed Aug 7 '17 at 22:10
  • \$\begingroup\$ If you have major timing violations or poorly constrained design, implementation can take much more than it needs to \$\endgroup\$ – Claudio Avi Chami Aug 7 '17 at 22:14
  • \$\begingroup\$ What kind of machine do you have? (The primary numbers of interest being number of cores, RAM, and clock speed). Also, what does "take a while" mean? 10 mins? 40 mins? 4 hours? \$\endgroup\$ – uint128_t Aug 8 '17 at 3:49

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