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I am curious if this could work. I have 3 inputs (A,B,C) and I know that Input A takes the longest to calculate.
Is it possible to use single Transistors in place of normal AND Gates so that a signal from A will have less propagation delay (if any?) to reach the Output? How long would the delay be relative to normal AND gates? Can I make this chain as long as I want?

schematic

simulate this circuit – Schematic created using CircuitLab I drew this schematic according to my best understanding of how transistors work. I assume the line between A and Out has to be drained before A signal from A can be interpreted correctly at Out.

If I am wrong please explain why this would not work.

Edit1:
I seems I have confused a lot of people by using the wrong kind of schematic symbols. Just to clarify I am talking about the the kind of transistors that one would find in a CPU, mainly the ALU part.

schematic

simulate this circuit

I have made some adjustments to my previous schematic in order to highlight what I mean. I have removed "EnergyDrain" and instead now use B to drain the current.
These two circuits are supposed do the same thing. I am interested about the AND gate on the left.
As I see it the circuit on the right has less transistors as the circuit on the left and A does not need to trigger a transistor itself. I just don't understand why this design would not be faster than the normal design.

Should I open a new question for this? I am new to this forum so I apologize if I am do not know all the guidlines too well.

Edit2: Fixed symbols in Edit1 as "mkeith" has suggested in the comments.

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  • \$\begingroup\$ What is "EnableDrain" supposed to represent? \$\endgroup\$ – duskwuff Aug 8 '17 at 0:02
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    \$\begingroup\$ Please explain, in significant detail, why you think your circuit works and how it is supposed to work. Then perhaps someone might attempt to explain why it would not work. You go first and make a good argument, though. \$\endgroup\$ – jonk Aug 8 '17 at 1:22
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    \$\begingroup\$ In your revised circuit, "and gate with less transistors," the source of the PMOS is connected to the output. This means that the state of the transistor depends on the output voltage. I don't think this is desireable. If the output has a 10k resistor to GND, and it is low, no combination of inputs will ever be able to drive it high. I assume it was an error to connect the positive terminal of the voltage supply to GND. \$\endgroup\$ – mkeith Aug 8 '17 at 8:16
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    \$\begingroup\$ The circuit you refer to as a normal AND gate is basically a NAND gate, but you connected the PMOS wrong. The sources need to be closer to VCC for it to work correctly. Sources should not be connected to outputs. In other words you accidentally reversed source and drain. Maybe that is what you did in "and gate with less transistors" too. \$\endgroup\$ – mkeith Aug 8 '17 at 8:20
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    \$\begingroup\$ So, if I assume the power supply is hooked up wrong, that GND is the negative rail, and assume your FET is backwards by mistake, then the truth table for your circuit is as follows: (A,B = 00 -> 0; 01->0; 10->1; 11->0. So that is not the truth table for AND or NAND. However, with those assumptions, I believe it would work to give this alternate truth table. The only real problem is that the A input is loaded by whatever is attached to the output. Normal gates do not transfer the output load back to the input. \$\endgroup\$ – mkeith Aug 8 '17 at 8:32
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I think what you are thinking about is pass-transistor logic, and though I believe it's not very popular, it exists and may make sense in some cases. In fact, I've used it in a laboratory course to design a 16-bit multiplier.

To overcome the issue with the gate-source voltage threshold (preventing the output voltage to reach both rails), the logic uses complementary pairs with one input inverted, like this:

schematic

simulate this circuit – Schematic created using CircuitLab

That way, the pMOS will pass a 'strong' (meaning that it will conduce at its best) 1 and the nMOS will pass a 'strong' 0. Note that you only need 4 transistors for an AND gate, instead of the 6 (4 for NAND + 2 for NOT) needed with traditional CMOS push-pull logic.

The main issue with pass-transistor logic is that you are adding a resistive path to the 'A' signal, which will load its driving gate together with the fan-out of A&B. Therefore it should be used wisely, and may eventually not be convenient.

Also note that you can (in theory, YMMV) mix up pass transistor logic with push-pull logic.

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  • \$\begingroup\$ Yes, that was exactly what I was looking for! \$\endgroup\$ – Rasilu Aug 8 '17 at 10:27
  • \$\begingroup\$ So is there any advantage to this logic in terms of speed? And if I would chain some of these 'gates' together, how far can signal A travel, before it is no longer determinable (1, 10, 100 .. 'gates')? Could I improve any of these two factors by changing voltage on signal A? \$\endgroup\$ – Rasilu Aug 8 '17 at 10:33
  • \$\begingroup\$ Should I maybe open a new Question now that I know what I am talking about so I can formulate it better? It feels to me like it would be bad practice if I edit the question too much. @clabacchio \$\endgroup\$ – Rasilu Aug 8 '17 at 10:56
  • \$\begingroup\$ @Rasilu now that you have found the name, it would be better to research a bit on the topic before asking further questions, so that you have more comprehensive knowledge on it. About how many you can cascade, virtually infinite but then switching transients become prohibitive and worse than push-pull ones \$\endgroup\$ – clabacchio Aug 8 '17 at 12:10
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    \$\begingroup\$ @mkeith it all boils down to an RC transient with the fanout capacitance and the line plus source-drain resistance to limit the current (plus other parasitics). Stacking too many pass-transistor gates can significantly affect performance, but it depends on technology and logic to implement \$\endgroup\$ – clabacchio Aug 8 '17 at 16:26
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enter image description here

Admittedly "Old School", but it works.

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  • \$\begingroup\$ But this will be slower than a standard and gate. Not faster. \$\endgroup\$ – mkeith Aug 8 '17 at 4:46
  • \$\begingroup\$ This kind of defeats the purpose of the question tho \$\endgroup\$ – Rasilu Aug 8 '17 at 6:54
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A normal and gate is built out of several transistors all grouped together on a single integrated circuit. You could possibly duplicate the functionality with discrete transistors, but the end result will not be faster in propagation delay than the integrated circuit. A big reason for the delay is that transistor inputs have capacitance, and the wires that connect them have inductance. The capacitances and inductances are much smaller in IC's than in discrete designs. So the delay will only be longer.

A CMOS AND gate is a NAND gate followed by an inverter. The NAND gate uses 4 transistors. The inverter uses 2. Here is a diagram of a NAND gate.

NAND gate schematic

https://en.wikipedia.org/wiki/NAND_gate#/media/File:CMOS_NAND.svg

There are some reasons why it is not ideal to try to do this with discrete transistors. Mainly if the PMOS on top turns on at while the NMOS on the bottom is on, you will have large shoot-through currents. So you have to make sure that doesn't happen, or use resistors to limit the current.

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  • \$\begingroup\$ In CMOS logic circuits, PMOS is always on top (between VCC and output), and NMOS is always on bottom (between output and GND). \$\endgroup\$ – mkeith Aug 8 '17 at 4:48
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Vgs thresholds, Vdd and RdsOn are critical design parameters when you have Complmentary MOSFET designs.

Vil, Vih input thresholds and Vol, Voh needs to be controlled swings and meet timing criteria to be relevant.

The Gate voltage needs to be at least 2x Vgs threshold to get reasonable RdsOn and preferably 3x. The input capacitance and load factors need to be minimal for speed and the output voltage needs to comply with CMOS standards at rated load and Vdd.

This 2 transistor design does not not meet any of the above criteria but a small picture can show why using 2 different clks for inputs.

enter image description here

My simulation here

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  • \$\begingroup\$ So if I understand it correctly, the signal coming from A does not have enough voltage to travel through my design and still be read correctly at the output? What would I need to change in my design to fix that? \$\endgroup\$ – Rasilu Aug 8 '17 at 7:56
  • \$\begingroup\$ too high impedance for non-inverting inputs both high and , both FETs off, results in weak pullup.. So all CMOS are buiffered and have low impedance outputs at all times for lowest RC = T slew rates. \$\endgroup\$ – Sunnyskyguy EE75 Aug 8 '17 at 8:05
  • \$\begingroup\$ Ah yeah, that makes sense. I don't think I understand everything but I think I got a general idea about why my design would not work as it is now. \$\endgroup\$ – Rasilu Aug 8 '17 at 8:12
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You don't need a transistor for an AND gate design.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ This will be slower than a standard and gate, though. \$\endgroup\$ – mkeith Aug 8 '17 at 4:45

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