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I plan to create a circuit that communicate with 28 UART channels (115,200 bps for each channel). Can you advise what could e the best architecture to create this type of circuit? Let say that those are the controller communication protocols: USB channel, 3 SPI channels, 2 UART channels, FlexCAN, PCIe, I2C and Local bus

I thought about using MAX14830 which is a quad uart component, controlled by SPI. By using 7 components like this, I can create 28 UART channels, controlled by 3 SPI channels (using CS to choose with which uart quad to communicate with, and then control each time with each of the UART channels to use)

My question is if you have more elegant ways to do that using one of the other communication protocols I mentioned. Thanks.

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  • \$\begingroup\$ Are you saying you want a micro with USB, 3 SPI channels, 2 UART channels, FlexCAN, PCIe, I2C and Local bus and then 28 external UARTs? Or the interface to the UARTs could be USB, 3 SPI channels, 2 UART channels, FlexCAN, PCIe, I2C and/orLocal bus? \$\endgroup\$
    – DiBosco
    Commented Aug 8, 2017 at 14:15
  • \$\begingroup\$ Let say I have a micro controller with all of those interfaces and I want to convert some of them to UARTs (so wi will have evantually 28-30 uart channels) \$\endgroup\$
    – Dudi
    Commented Aug 9, 2017 at 5:48

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In terms of elegance, I would say an FPGA. It's relatively straightforward to set one up with loads of UARTs, especially if they're all at the same baud rate etc and you could connect them via local bus or maybe even SPI bus[es]to get the data in with a DMA. However, you have to be sure that your micro can cope with processing 28 channels of serial data at the same time! You'd also need to check the FPGA had enough memory to have half decent buffers as you're looking at a maximum of 315k bytes of data per second if all those UARTs are going full pelt.

You could even use a NIOS soft core and do it all in one.

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  • \$\begingroup\$ Thanks, I will look for Xilinx FPGA that can do that and investigate NIOS soft core. \$\endgroup\$
    – Dudi
    Commented Aug 9, 2017 at 10:58
  • \$\begingroup\$ I don't know anything about Xilinx for purely historic reasons (I have nothing whatsoever against them), but NIOS is an Altera thing. I would be surprised if Xilinx didn't do a similar thing though. \$\endgroup\$
    – DiBosco
    Commented Aug 9, 2017 at 11:02
  • \$\begingroup\$ Since im not so familiar with the FPGA world, can you guide me on what paramaters should I look for in order to know if the chip can handle 28 channels of UART? \$\endgroup\$
    – Dudi
    Commented Aug 9, 2017 at 11:08
  • \$\begingroup\$ You need to get an idea about how many logic elements are needed to implement a UART on a particular platform (including some buffer space). Then multiply that by 28. There are cool sites like opencores where you can get this sort of idea IIRC. I'd guess for something like a UART Xilinx and Altera might have their own IP they give away too. \$\endgroup\$
    – DiBosco
    Commented Aug 9, 2017 at 11:15
  • \$\begingroup\$ @DiBosco fyi Microblaze is Xilinx's version of NIOS. \$\endgroup\$
    – Colin
    Commented Aug 9, 2017 at 13:11

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