While going through the document at https://www.silabs.com/documents/public/application-notes/AN639.pdf I have read from "Figure 13. Loop Antenna Simulated Mag(Zin) vs. CP1" below that even a 2% tolerance for Cp1 results in a Zin of about 200 - 250 Ohm for the 434 MHz frequency range that I am heading for. The desired Zin is 500 Ohm.

I am not sure if this is the case but as I understand it this will cause a good fraction of the power to be reflected back into the IC. If so, could I have a maximum tolerance level for Cp1 so that my transmitter will not require full power in order to cover a mere few meters ? (in ohter words, for my transmitter not to perform poorly)

enter image description here

  • 3
    \$\begingroup\$ anytime Q=350, component tolerance on f and Zin is going to be very tight. as it is inverse to the Q. Dont forget dielectric tolerance of 10% ... go for the 55mm square and 15dB return loss and work out the tolerances. Otherwise, just use a 1/4 lambda wire. which will work for that range and tune length \$\endgroup\$ – Tony Stewart EE75 Aug 9 '17 at 1:34
  • \$\begingroup\$ @TonyStewart.EEsince'75 Ok, is the dielectric with the 10% tolerance the PCB's dielectric ? If it is, isn't most of the electrical field radiated by this antenna formed between its two sides of the loop, so air would be the dielectric ? What is a '55 mm square' ? \$\endgroup\$ – kellogs Aug 9 '17 at 10:34
  • \$\begingroup\$ FR4 is inside the loop and this also affects self resonant freq. with e~4 +-10% . Datasheet shows dBi gain is max for 55mm square loop -3dBi ? as I recall, which is an indication of losses. Coupling to free space impedance affects far field levels with air as a diectric. The velocity factor for tuning L of V.F. 0.82 is prrof of this interaction. \$\endgroup\$ – Tony Stewart EE75 Aug 9 '17 at 14:25
  • \$\begingroup\$ Don't expect to find a standard-size capacitor to tune this structure without having to add some PCB trim capacitance. As the app-note (and Tony) imply: calculate, build, measure....probably will take more than a few iterations. \$\endgroup\$ – glen_geek Aug 9 '17 at 14:41
  • \$\begingroup\$ Okay, thanks you both,but I am not going to go through all the theory and test iterations. I shall stick with the given design which has all been set up optimally. My question was related to that final tuning cap Cp1. Let me rephrase it: How much power will I lose if instead the optimum 500 Ohm impedance I ended up with a 250 Ohm impedance ? How would I calculate that ? \$\endgroup\$ – kellogs Aug 9 '17 at 15:29

ente image description here

Here a 55mm square loop gives the highest gain using 0.8mm FR4

Reducing area 50% correlates with ~3dB loss each time from this.

The author's calculation of v.f.= 0.82c is an indication of FR4 dielectric effects on wavelength and C values required.

Contrary to what the author says, the shunt capacitance controls a parallel resonant pole and not the series zero.

Here is my simulation. enter image description here

You can play with the values and aim at peak to get a reading. Note how phase changes abruptly at series resonance.

THe 1 Ohm ground shunt measures current and the Out before the cap measure transfer function while moving out to the 1 Ohm measures Zin. Q here is about 320 or 42.73dB gain limited by Series ESR and sense R ratio as well as X(f) for a crude approximation... set to 434 MHz.

Here showing the effects of a shunt C with a notch in radiated power by parallel resonance which comes closer to series f with larger C values.

enter image description here


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.