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I have looked across a few DDR3 IC's from different companies and different densities with the same data bus width, and they all seem to have the same packages (dimensions, ball pitch, etc) including what balls correspond to what function (excluding the top address bits for different densities).

Is this because there is a (convention?, JEDEC?) standard for what package and pads are used for various densities/bus widths of DDRn memory? I am asking because I am wondering if I can design a footprint for a project of mine that I can assume will work when populated with different (timing and density) DDR3 IC's assuming the following:

  • Data bus width is the same.
  • All the necessary address lines are connected.
  • I have the ability to configure the DRAM controller.
  • Routing can handle the potentially faster speeds of a different IC.
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    \$\begingroup\$ Yes there are standards for physical layout, impedance controlled tracks and track latency skew. ( equal length) jedec.org/document_search?search_api_views_fulltext=jesd235 \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 9 '17 at 1:12
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    \$\begingroup\$ Never forget the wealth of information available from Micron: Google: "micron ddr design guide" \$\endgroup\$ – Peter Smith Aug 9 '17 at 6:51
  • \$\begingroup\$ @TonyStewart.EEsince'75 Could you make your reply be an answer so I can mark it as such? \$\endgroup\$ – hak8or Aug 15 '17 at 6:44
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Yes there are standards for physical layout, impedance controlled tracks and track latency skew, physical, functional layout etc. https://www.jedec.org/document_search?items_per_page=60&search_api_views_fulltext=ddr3

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