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I was doing some research on Phase Locked Loops (PLLs). Now what I understand is, that the Loop Filter is first necessary to suppress unwanted signals on the VCO, so the tuning is controlled by the DC value of the Phase-Freqency-Detector (PFD). So the loop filter is a low pass filter and of course you want a low cutoff frequency \$f_c\$ for this reason.

Now to the second influence of the Loop Filter: If \$f_c\$ is low, the PLL will take longer to lock. But I don't understand this, how can the bandwidth determine the lock speed?

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  • \$\begingroup\$ Well, assume the loop filter was extremely slow. How long would it take the VCO output to change enough to match the input signal so that it can lock? \$\endgroup\$ – John D Aug 9 '17 at 21:32
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The lock speed, if far off frequency, is simply the time to charge that loop filter capacitor to be near the final frequency, whereupon the standard 2nd order loop dynamics will occur.

If far off frequency, the PFD will provide a beatnote of charge injection; thus a 1MHz frequency diffenence will display a 1MHz beatnote with 50% duty cycle.

If the Iloop is 100uA, then 50% of that is available to slew the Capacitor voltage.

A 1uF cap, give 50uA current, will slew at dV/dT = I/C = 50 volts/second.

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