I was doing some research on Phase Locked Loops (PLLs). Now what I understand is, that the Loop Filter is first necessary to suppress unwanted signals on the VCO, so the tuning is controlled by the DC value of the Phase-Freqency-Detector (PFD). So the loop filter is a low pass filter and of course you want a low cutoff frequency \$f_c\$ for this reason.
Now to the second influence of the Loop Filter: If \$f_c\$ is low, the PLL will take longer to lock. But I don't understand this, how can the bandwidth determine the lock speed?