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I would like to run a code on my FPGA (xilinx Zynq zc702)but it got stuck in the middle of the code . After investigating, I figured out that it must be a memory problem because I am declaring a double table ([2560]) and when i minimized the size of this table and just used table[102] the code works well

Would you please give me some ideas about how to increase the memory.

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  • \$\begingroup\$ What kind of "code" are you running, and how? Is this code running on the Zynq PS or PL? If it's on the PS, is there an OS running, or is it in a pre-boot environment? \$\endgroup\$ – duskwuff Aug 9 '17 at 23:09
  • \$\begingroup\$ @duskwuff i used a c code which i run in Xilinx SDK and the hardware is done in ViVADO \$\endgroup\$ – meri Aug 10 '17 at 7:44
  • \$\begingroup\$ None of that answers the questions I asked… \$\endgroup\$ – duskwuff Aug 10 '17 at 17:09
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Put in a memory interface in the FPGA logic and then strap an external RAM chip onto the side of the FPGA. Using static RAM (SRAM) for this is the easiest to implement. If you need a nonvolatile solution use a FRAM chip that has a parallel interface.

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The zc702 comes with 1GB of DDR3 on the board.

There are lots of available reference designs that you can download to learn how to implement the ram if you're having trouble: here's one

See page 126 of UG585 for memory connections.

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  • \$\begingroup\$ I tried to modify the DDR configuration and in the memory part configuration i change the DRAM IC Bus Width to 32Bits and the DRAM device capacity to 8192 MBits but nothing change so i was wondering is there anything should i modify in thos memory part configuration or i shouuld add BRAM memory ? \$\endgroup\$ – meri Aug 10 '17 at 9:53
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The problem is, your double table is synthesized to a logic function on the fpga. There is somewhere a option in the settings where you can choose SRAM for your LUT implementation

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