I was assigned a task where I have to connect an LTC2323-12 ADC (analogic to digital converter) to an FPGA.
Reading the LTC2323-12 datasheet seemingly it has two ways to be controlled. One way is through the SCK (clock-like) input that cycle by cycle shift the ADC results out of the ADC to SDO port.
The other way is described as a "high speed" that can "ease the timming requirements for the FPGA" (would you clarify this for me?) , this last one method is trough the CLKOUT signal, which is seemingly a Clock that comes out of the ADC that is matching (or latching) the ADC results out of the SDO port. Is that correct? Did I get it correctly?
So do I have to design the FPGA module in order to output the CNV signal of startup, then keep it for TCNVH nanoseconds, then release it, then just wait until ADC AUTOMATICALY send the first CLKOUT, so I can register it and count 11 more of these CLKOUT, while passing the SDO data out to my own registers on each of these CLKOUT cycles?
Then after the last 14 CLKOUT clocks, I must design a counter that trigger a valid signal that will start another counter of TDSCKLCNVH nano seconds, and at the same time porting out of this register register and a "Finishing" signal (so another top module with the same clock than my fpga module, can make use of these signals in another moment.
I would like you to correct me if I misunderstood something about the behavior of the LTC2323-12 ADC and the way to approach it. Thanks in advance.