I have reset synchronizer in my top block (attached file). In my project I have blocks which get 125_clk, and others 250_clk. In addition I have srstn_sm block which its output is input for srstn input of many blocks (attached file).

The code for the srstn_sm block:

entity srstn_sm is
generic(
reset_duration_cc_g : positive := 10
);
port(
clk         : in  std_logic;
sft_srst_in : in  std_logic;
srstn       : in  std_logic;
srstn_out   : out std_logic
);

-- Declarations

end srstn_sm;

architecture behave of srstn_sm is

type   sm_states is (IDLE, RST);
signal sm_state  : sm_states;
signal srstn_cnt : natural range 0 to reset_duration_cc_g;

begin

srstn_sm_proc : process(clk)
begin
if (rising_edge(clk)) then
if (srstn = '0') then
srstn_out <= '0';
srstn_cnt <= 0;
sm_state  <= IDLE;
else
case sm_state is
when IDLE =>
srstn_out <= '1';
if (sft_srst_in = '1') then
srstn_out <= '0';
srstn_cnt <= srstn_cnt + 1;
sm_state  <= RST;
end if;

when RST =>
if (srstn_cnt = reset_duration_cc_g-1) then
srstn_out <= '1';
srstn_cnt <= 0;
sm_state  <= IDLE;
else
srstn_cnt <= srstn_cnt + 1;
end if;
end case;
end if;
end if;
end process srstn_sm_proc;

end architecture behave;


As both clocks are in phase and one clock is an integer division of the other, I want to synchronize the reset to the slower clock, because every rising edge on the slow clock will also be a rising edge on the fast one. Should I inesrt 125_clk/250_clk to the srstn_sm block?

How the requirement time is calculated in each case?

What if this reset (which is syncronized by 125_clk) is an input for block which gets 250_clk. It the requirement time will be 4ns or 8ns? Should I handle this in a special way (multicycle_path or something else...)?

• The task of a reset synchronizer is to synchronize a reset signal from one clock domain to the other and implement some specialties for resets. So at first, if both clocks are related to reach other, you don't need such a circuit. At second if the are unrelated, then your circuit doesn't handle the metastability problem, which is the main reason why you need a synchronizer. A synchronizer will always need the output clock, and some may also need the input clock to capture the data before synchronizing. – Paebbels Aug 12 '17 at 5:49
• You can find a set of synchronizers here: poc-library.readthedocs.io/en/latest/IPCores/misc/sync/… – Paebbels Aug 12 '17 at 5:49
• @Paebbels - the sm clk works with 125_clk, where the second block which gets the srstn_out as input works with 250_clk. – sara r Aug 13 '17 at 7:54
• @Paebbels - the syncronized reset is on top level. The srstn_sm block works with 125_clk. Its output (srstn_out) insert to various blocks. and some of them work with 250_clk. So the question is - Is the requirement time will be 4ns or 8ns? Should I handle this in a special way (multicycle_path or something else...)? – sara r Aug 13 '17 at 8:26