I have reset synchronizer in my top block (attached file). In my project I have blocks which get 125_clk, and others 250_clk. In addition I have srstn_sm block which its output is input for srstn input of many blocks (attached file).
The code for the srstn_sm block:
entity srstn_sm is generic( reset_duration_cc_g : positive := 10 ); port( clk : in std_logic; sft_srst_in : in std_logic; srstn : in std_logic; srstn_out : out std_logic ); -- Declarations end srstn_sm; architecture behave of srstn_sm is type sm_states is (IDLE, RST); signal sm_state : sm_states; signal srstn_cnt : natural range 0 to reset_duration_cc_g; begin srstn_sm_proc : process(clk) begin if (rising_edge(clk)) then if (srstn = '0') then srstn_out <= '0'; srstn_cnt <= 0; sm_state <= IDLE; else case sm_state is when IDLE => srstn_out <= '1'; if (sft_srst_in = '1') then srstn_out <= '0'; srstn_cnt <= srstn_cnt + 1; sm_state <= RST; end if; when RST => if (srstn_cnt = reset_duration_cc_g-1) then srstn_out <= '1'; srstn_cnt <= 0; sm_state <= IDLE; else srstn_cnt <= srstn_cnt + 1; end if; end case; end if; end if; end process srstn_sm_proc; end architecture behave;
As both clocks are in phase and one clock is an integer division of the other, I want to synchronize the reset to the slower clock, because every rising edge on the slow clock will also be a rising edge on the fast one. Should I inesrt 125_clk/250_clk to the srstn_sm block?
How the requirement time is calculated in each case?
What if this reset (which is syncronized by 125_clk) is an input for block which gets 250_clk. It the requirement time will be 4ns or 8ns? Should I handle this in a special way (multicycle_path or something else...)?