This is kind of a follow-up to this question: Current to Voltage Feedback Capacitance for SiPM

I'm working on another trans-impedance amplifier circuit. The basic schematic is shown below:


simulate this circuit – Schematic created using CircuitLab

In this design, I am trying to place two identical trans-impedance amplifier circuits on the same PCB board. Both of these circuits are independent of each other, with each circuit drawing power independent of each other through its header. I've worked on previous boards like this, and you can see in my previous question that things haven't worked out so well. Now, I'm trying to design it better this time, but I wanted to address some concerns that I have.

In my previous design in the previous question, the circuit had four SiPMs laid out on one board, and they can be split up into four independent channels or two channels with 2 SiPMs in each channel. This board was a bit of a mess. The 6-layered board had issues with crosstalk, so we're trying to go back to the basics with one SiPM per channel. Also, each channel is powered independently by their own power source so there should be no interference among them

Some of my concerns regarding this new design is this:

  1. Even though each SiPM and amplifier are independently powered through their own header, is it fine for them to share the same GND plane?

  2. The number of layers can be as small as 2, but is it better to go for more layers? You can see below a first draft of how one circuit is laid out. I would have one channel be on one end of the board (a rectangular 50 mm length board) and the second channel on the other end. The SiPM is designed such that the two cathode pins are on opposite corners of the board, so I went with four layers in the following order:

  3. Top layer -- In red, use to connect to Anode

  4. Inner Layer 1 -- In yellow, use to connect cathode pins
  5. Inner Layer 2 -- In pink, use to connect power pins
  6. Bottom layer -- In green, amplifier and parts.

Proposed Connector

All of the layers are GND planes. If I go for six layers, I can put two GND planes to isolate layers even further. If I do that, aside from cost, would that help with signal integrity and help prevent crosstalk? Where would it be best to place these planes?

  1. Layout. I tried to place the parts as close as I could so as to avoid interference and to make the signal faster. Is there anything that can be improved with this proposed layout? What really concerns me is the via in the middle of the SiPM going from the cathode to the amplifier. It's in the middle of four pads connected to GND. A slip of the hand on this BGA part can unintentionally short something, so this location might not be the best idea. Also, this may not happen due to design limitations by Advanced Circuits, the PCB board maker. Shorter is better for faster signals, but what else would be an ideal placement?

I understand that vias would have to be placed around the board to reduce the inductance, but right now, I'm just trying to lay things out. If there's any other concerns that I should address, please let me know.

The photomultiplier is a SensL MicroFJ-60035-TSV photomultiplier, and the amplifier is a TI OPA656 amplifier. The header is a 4-pin connector.

  • \$\begingroup\$ What is U1 in the layout? \$\endgroup\$ – The Photon Aug 11 '17 at 16:37
  • \$\begingroup\$ @ThePhoton U1 is the photomultiplier. \$\endgroup\$ – user101402 Aug 11 '17 at 16:41

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