I'm trying to implement the following design in VHDL:

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My teacher said that I can replace the MUX with a shared bus, so I can use an Output Enable signal to control what is on the bus, however, I don't know how to achieve this with VHDL.

  • \$\begingroup\$ Each of the drivers on the bus can have CS (chip-select) or OE (output enable) pin, which will drive it's output to a high-Z when not selected. \$\endgroup\$ – Eugene Sh. Aug 11 '17 at 13:56
  • \$\begingroup\$ isn't that almost exactly the same as muxing it (in this particular case)? Does he gain any gates by doing it with a shared bus? \$\endgroup\$ – Harry Svensson Aug 12 '17 at 0:24
  • \$\begingroup\$ I am sorry to tell this in blunt terms but your teacher is a zero, as sadly many teachers are, and have no idea whatsoever of what is inside an FPGA these days, as also happens with many teachers. Probably he learned something 10 or 15 years ago and keeps teaching what was used 10 or 15 years ago. You can also read more about this issue in this entry on my blog fpgasite.blogspot.co.il/2017/05/… - And you can tell your teacher what I think. Luckily it may move something in him/her and force him/her to actualize and stop teaching crap. \$\endgroup\$ – Claudio Avi Chami Aug 12 '17 at 6:35

No, you CANNOT replace a MUX on an FPGA with a shared bus because NO FPGA (nor ASIC) in the market have internal shared buses of any kind.

You can try to write the logic to implement a shared bus, and one of two things will happen:

1) The synthesizer will reject your VHDL, or

2) The synthesizer will replace your tristate drivers with... MUXes

So you will take a long road where at the end, you will receive what you started with: MUXes.

  • \$\begingroup\$ The question is if the user wants to write the model on a real FPGA or only simulate the VHDL model. In the second case the question is if VHDL supports shared busses (although the model can only be simulated and not be written to a real FPGA in this case). \$\endgroup\$ – Martin Rosenau Aug 12 '17 at 10:20
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    \$\begingroup\$ @MartinRosenau a model for shared buses can be written in VHDL, but we don't write in VHDL for the fun of it, we learn and strive to write SYNTHESIZABLE code (unless you are writing a testbench, but this is not the case). \$\endgroup\$ – Claudio Avi Chami Aug 12 '17 at 12:48
  • \$\begingroup\$ As far as I understood it is for some university project. In university projects the goal is sometimes to design an ASIC (which would not be produced in the case of an university project) and not FPGA code. \$\endgroup\$ – Martin Rosenau Aug 12 '17 at 12:54
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    \$\begingroup\$ @MartinRosenau there are no tri-state buses on an ASIC either. Or maybe I should say, their use is not recommended for many years now. I think a teacher should recommend a student to improve solutions, not to degrade them. The student used a good solution and the teacher is asking him to replace it for a crappy one. \$\endgroup\$ – Claudio Avi Chami Aug 12 '17 at 13:06
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    \$\begingroup\$ "ASIC" means nothing other than: Custom chip. The word does not even say if the IC is analogue or digital. You might produce an IC containing an 6502 CPU and an 4118 SRAM on one part of silicon. This would be an "ASIC" then. The "data" lines (D0-D7) between the 4118 and the 6502 and to the IC's pins would definitely be tree-state on such an ASIC. \$\endgroup\$ – Martin Rosenau Aug 12 '17 at 15:08

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