# 32 kHz crystal not operating as expected

I've been trying to figure this issue out for a couple days now, reading up on typical crystal operation / configuration, and I'm at a loss. I tried searching here but didn't encounter anything similar to my issue, so I'm sorry if I missed my solution somewhere.

I'm trying to run an RTC off of an external crystal using a PIC, but the crystal isn't oscillating when I expect it to, and is oscillating under other circumstances, and I can't make any sense of it. I'm not an EE though, so I'm probably just being super ignorant.

The crystal: LFXTAL016178. I'm fairly certain that because nothing is listed, it's a parallel resonant crystal. Its load capacitance is 6 pF, which I've found to be sort of uncommon? I'm not sure.

The PIC: PIC24FJ128GB204. I've connected the crystal as the datasheet suggests, but it doesn't provide much explicit help in selecting load capacitors, so I did some searching and found other resources online to help me there.

The setup: I saw from a couple sources that a good rule of thumb for load capacitors is $C_L = \frac{C_1 × C_2}{C_1+C_2}$, adding stray capacitance to $C_1$ and $C_2$ of between 2 and 5 pF. I picked what I thought was a middle value of 6pF for both capacitors, and I'm still not sure how bad that selection was.

Here is a picture of my schematic: Layout:

Cases where it doesn't work:

• As it is in the schematic, with 6pF load capacitors on both pins, it doesn't oscillate. Unless it oscillates every 10 minutes or something.
• With the capacitors removed, it oscillates extremely slowly, maybe approximately 2.5 times slower than it should. I didn't measure this speed.
• With extra 6pF capacitors soldered on top to make 12pF capacitors, it doesn't oscillate.
• With 3 pF capacitors and a 10 MOhm resistor across the pins. (RTCC clock is erratic.)

Cases where it does work:

• When I probe the SOSCI pin with an oscilloscope. In the first three cases above, as soon as I touched the probe to the SOSCI pin, it started up and gave me a nice clean sine wave. It didn't do this when I touched the SOSCO pin, OR when I used 3pF capacitors. I know it wasn't working beforehand because of some LEDs that are supposed to blink every second, which only blinked with the probe connected. (I don't know everything about oscilloscopes, I just know how to operate them. The probe says 6MHz/1MOhm/95pF, and the scope says 60 MHz/1 GS/s and 300V CAT II where the probe connects. It's a Tektronix TDS 2002 if that means anything to anyone.)
• When I connect a 330 Ohm resistor between SOSCI and ground. It's one of two resistors I have on hand; the 10k looked like it made it operate at about half the right frequency.
• With 3 pF capacitors, but at 14 kHz.

Here are some frequencies that I've measured:

• (12 pF Caps) Frequency touching probe to SOSCI: 32.7674 kHz
• (12 pF Caps) Frequency output by PIC with the 330-ohm pull-down on SOSCI: 32.764 kHz
• (12 pF Caps) Frequency output by PIC using LPRC: 32.68 kHz
• (3 pF Caps) Frequency output by PIC: 14.08 kHz

Basically, what I'd like to know is why it oscillates perfectly sometimes when I use a scope probe, and what the correct solution should be in order to make it work as I want it to.

EDIT: I've only just found this application note, where it says that I should have selected a 12.5 pF $C_L$ crystal for my microcontroller. However, any crystals on Mouser/Digikey with my desired minimum operating temperature (-55$^{\circ}$C) are out of stock. I'll be getting one that will suffice for now, but I think my questions still stand.

EDIT2: With a fancy new crystal ($C_L$=12.5 pF) and some standard 22 pF caps, it worked at 32.7676 kHz. What does this imply about what went wrong with the old crystal ($C_L$=6 pF)?

• All that ground results in a larger capacitance. – Ignacio Vazquez-Abrams Aug 11 '17 at 22:31
• What if you put a fairly large resistor (between 300k and 4.7M, say) in parallel with the crystal? – uint128_t Aug 11 '17 at 22:38
• This PIC has a very configurable GPIO shared with XTAL pins. Are you sure you have the right I/O configuration in your software? – Ale..chenski Aug 11 '17 at 23:04
• Crystal oscillators are tricky. Did you check their working REFERENCE DESIGNS, for what kind of crystals do they use, and which one works? microchip.com/wwwproducts/en/PIC24FJ128GB204#tools – Ale..chenski Aug 12 '17 at 3:46

The MCU maker is likely at fault. There is absolutely no excuse for not designing a modern MCU RTC oscillator to reliably function with any typical commercially available 32kHz crystal.

Unfortunately, the opposite is much more common, as you have already discovered - in your case the MCU data sheet fails to mention that 6pF load capacitance does not work.

The root issue is that you are dealing with a system of two components, made by two different manufacturers. One of them speaks silicon and the other speaks quartz, and they have never properly agreed how to tell designers how their products reliably work together.

So, as you have found out, the crystal oscillator can be a trap for the unweary. I have seen a major automotive production line grind to a standstill because of crystal oscillator startup issues!

Anyways, to get to your question of WHY, there are four important parameters at stake:

1. Output impedance of the MCU oscillator. This varies over frequency and is often complicatated by configuration bits such as "drive level" or "power level". I have never seen these values specified/guaranteed by any MCU maker.

2. Input impedance of the external capacitor-crystal-capacitor "pi" network. This is primarily determined by the capacitor on the input side, which in turn is determined by the load capacitance specified by the crystal maker.

3. Voltage gain of the (loaded) MCU oscillator at resonance. The oscillator gain has to make up for the ESR-induced loss of the external Pi network. This gain changes significantly over temperature, supply voltage and manufacturing batch. I have never seen this gain (and driver output impedance) properly specified /tested/guaranteed by any CPU maker. Some makers specify transconductance $G_m$ instead of voltage gain.

4. Voltage gain (actually loss) of the external Cap-Xtal-Cap "Pi" circuit at resonance. This is primarily determined by the internal equivalent series resistance (ESR) of the crystal. The crystal you mentioned specifies ESR=50k. The resistance also increases over age (as moisture/impurties leak into the crystal case) and is also affected by soldering temperature/time. (Impurities in the crystal case evaporating & settling on the quartz) ESR can also vary significantly between manufacturing batches. 50k is a fairly typical ESR for a 32kHz crystal - the lowest I have seen specified at 32kHz for small form factor crystals is 30k.

For any oscillator to work, the total voltage gain, which is the the product of (3) and (4) must >1. In addition, the phase of the gain (yes, gain is a complex number) must be 360 degrees. About half of the phase, 180 degrees, is provided by the inverting amplifier, and the "second inversion" is provided by the cap-xtal-cap network.

Here's a simple online simulation that can help you get a feeling for how gain, output impedance and the capacitor values interact and affect startup. Right-click any component to change its value. (Note - this simulation uses 1mV residual capacitor voltage to fake startup, but in real life noise in the amplifier is the source of startup, like in this one)

So what happened in your case? Most likely, the MCU oscillator designer designed his output stage to reliably function with 12.5pF loaded crystals, and it turned out that at 6pF loading, either the voltage gain or phase requirements were simply not met. Since nothing about the design assumptions is stated in the data sheet, voila, problem for you - and many others.

Wow, what should an embedded designer do?

First, always be aware that a marginal crystal oscillator can cost your business a lot of money.

Second, in light of the above, especially if you lack experience or if your MCU vendor doesn't specify crystal parameters in the datasheet, your best investment could be an external low power 32kHz oscillator.

Third, ensure you use a crystal with ESR and capacitance specified by your MCU maker. If you don't see any in the data sheet, ask your supplier for a list of recommened crystal part numbers, or choose an MCU that does.

Fourth, test, test, test! Over all voltages and temperatures. Note how long startup takes by timing it in firmware using an RC clock if possible, and if production units exceed the norm by, say 2x, let your test firmware set a flag so it can be noticed in production testing. That way, production units can't get out the door with marginal oscillators without alarm bells ringing.

What do experienced production verification engineers do?

They work around the general lack of proper information by requiring a 10x safety margin between "what works" and "what works reliably" - they measure the actual ESR, then add an extra 10x additional "handicap resistance" in series with the crystal into the cap-xtal-cap network. If the "handicapped ESR" system works over all voltage and temperature combinations, then it's assumed that the 10x safety margin is sufficient to cover the unknown variabilities in both ESR and MCU gain. This is partially explained in figure 3 of this application note.

What should YOU do?

If you can't perform the above test for any reason and want to sell a product in thousands, you are certainly better off investing the extra pennies for an off-the-shelf 32kHz oscillator from an oscillator vendor who has done all that testing for you, or by switching to an MCU that specifies a specific crystal (or crystal requirements) in the device data sheet.

While you may "fix" the situation by selecting a crystal with lower internal resistance and/or by playing with different/asymetrical capacitor values, your solution could still be marginal, for the reasons explained above.

TL;DR:

Crystal oscillators can cost your business a lot of time and money. Use an external oscillator if you can, or peform the "handicapped ESR" test as described above over all voltage and temperature ranges.

Finally, be sure to use NPO capacitors for temperature stability.

• Lower ESR is good for AT cut AMD series mode but higher ESR like 50~70kohm is better than 30k for stability – Tony Stewart Sunnyskyguy EE75 Aug 20 '17 at 18:21
• If your application needs high reliability, I also recommend an external oscillator. If cost is a major factor, then I recommend the use of a "standard" LC oscillator, at the desired frequency, and use the crystal - only to stabilize it, not as the source of the signal. – Guill Aug 21 '17 at 1:02
• @TonyStewart - interesting, do you know the fundamental reason why that is so or do you have a good reference? – neonzeon Aug 21 '17 at 5:16
• @neonzeon my references are not handy but App Notes from OEM's testing various suppliers of 32.76kHz resonators indicate better stability at higher ESR. IQD state that their ultra low tolerance low power XO's have no App Notes for their Xtals. Yes specs for best 10 ppm 32kHz parts specify ESR=70k AND 0.1uW +\- 0.01 uW drive level with load C down to 6pF options. This implies one should not even using the OP' design with copper pour nor 5V nor without Rs – Tony Stewart Sunnyskyguy EE75 Aug 21 '17 at 13:24
• I may be wrong in above assumptions about ESR, ti.com/lit/an/slaa322d/slaa322d.pdf#page12 indicates highest SF margin at 35k and lowest at 70k so perhaps the higher ESR function ...with lower power stated at IQD as 0.1uW 10% and 0.5uW max while others are 1uW max, so lower ESR is good for margin and high ESR enables lower power – Tony Stewart Sunnyskyguy EE75 Aug 21 '17 at 18:29

There are two main things going on:

1. You don't have enough load capacitance.

2. You don't understand load capacitance.

Imagine one side of a crystal being driven with a sine wave at the crystal frequency. This signal is low impedance. The load capacitance is that capacitance you put on the other side of the crystal to cause a 180° phase shift.

The phase shift of such crystals varies quickly as a function of the frequency at the crystals operating frequency. Since the phase as a function of frequency is very steep right at the operating frequency, this is a good thing for the driving circuit to use to ensure the crystal is operating at the intended frequency. These types of circuits oscillate optimally when the crystal shifts the input phase by 180°. Since only a little frequency change messes that up, the resulting oscillation is very close to the crystal's intended frequency.

Now back to your circuit. The big clue is that things work when you put a scope probe on the oscillator input pin. What that is doing is adding capacitance on the output side of the crystal. Apparently, with the setup you have, the additional scope probe capacitance causes the crystal to shift the phase the appropriate amount for the system to oscillate. If you add more capacitance yourself to the crystal output only, you replicate the effect of the scope probe and things will work. Try another 10 pF or so for starters.

Don't use formulas you find on the other end of the internet without understanding them. The equation you show makes a bunch of assumption, some of them not valid. Unfortunately there is a lot of conventional stupidity out there regarding crystals.

The crystal by itself is only a two-terminal device and doesn't "know" anything about your circuit ground. Ultimately, the load capacitance is what is across its terminals. The conventional stupidity therefore says to use two equal capacitors on each side of the crystal to ground. Since these are in series, each need to be twice the desired capacitance. However, whatever stray capacitance to ground you think there is on each side of the crystal needs to be subtracted from these capacitances.

The problem with the conventional stupidity is that it ignores the impedance of the crystal driver output. Consider the extreme case where that is 0. In that case, the capacitance added on the input side of the crystal is completely irrelevant, since it is in parallel with the 0 impedance of the driver. The load on the crystal is then only the capacitance on its output.

Do some math. The impedance of 6 pF at 32.8 kHz is 810 kΩ. Now the impedance of the crystal driver is certainly not zero, but quite likely significant relative to 810 kΩ.

Consider what each of the caps really do. The one on the input loads the crystal driver. The main purpose of that is to attenuate some of the harmonics coming out of the driver. This beats on the crystal less, and makes it less likely that the whole system will oscillate at a harmonic. Crytals have complex transfer characteristics. They can have some of the same characteristics at harmonics as they do at the intended operating frequency. Some crystals are cut so as to deliberately enable use at harmonics, called overtone mode in the industry.

The capacitance on the output is the true "load" capacitance. Its reactance works against that of the crystal to phase shift the result the right amount at the right frequency.

In your case, the crystal is rated for 6 pF load, and that's what you put on its output. That should have worked. My guess what is happening is that the cap on the input of the crystal, really on the output of the crystal driver, also caused a phase shift that worked against that of the load cap. Just as a test, try removing the cap on the crystal input and leave the 6 pF on its output. It would be nice to see the waveshape on the crystal input then, but even a 10x scope probe might change it. Try it anyway, but make sure the scope probe is set to the highest impedance, therefore the lowest capacitance, possible.

• Most overtone crystals are exclusively for >10MHz not 0.32768 MHz due to size. Also explain what happens to Q, when the output low impedance is driving the crystal CLC parallel resonant mode without a series R. – Tony Stewart Sunnyskyguy EE75 Aug 20 '17 at 15:18
• I think 2. is correct but 1. is not. the trace gap load cap is too much and not split so that it allows the 1st cap to create a transmission LPF and prevent feedthru capacitance across resonator. reconsider pls – Tony Stewart Sunnyskyguy EE75 Aug 21 '17 at 18:17

The two caps and crystal operate as a 180 degree phase shift. The magnitudes of the two caps (ratio) will define the voltage transfer ratio. 6Pf sounds a little small, the issue is what is the crystal parallel load design point? You don't want to move far from this value. I typically have 27pf on each side.

I also see one sode if the crystal tied directly to the processor output. This output might be low Z which which can over drive a crystal. Remember this drive spec of these watch crystals is tiny, very easy to over drive. A series R of 100K can be used to reduce crystal drive.

Make sure the processor has in internal 1 - 10 Meg bias resistor from output to input. You mentioned it starts to oscillate when touched with a scope prob. That might be a DC bias issue (10Meg scope probe I guess) or probably the probe cap adjusting the tuned circuit transfer ratio.

Be really clean (no stray flux) and really short wires. It is a real Hi Z circuit.

Bob K.

Also: The "Standard" probes I use are x 100 as they provide the smallest amount of capacitance, I recall about 1.5pf. Using x 10 is difficult on this circuit, x 1 is useless. Ues x 100 and crank up the scope vertical gain, make the scope front end do its work. X 1 probes are almost useless for high Z or high speed. You will love the x 100 doing digital works as the GND clip currents are down by a factor of 10. Try It.

• The only answer I could find about the internal resistor was that the primary oscillator pins have one that is 2-10 MOhms, and that the secondary oscillator pins have one. – Andrew Elliott Aug 18 '17 at 16:42

At 32KHz, these are not typical XT/AT-cut crystals, but instead are digital-watch crystals, tiny "tuning forks" a few mm long.

Since it responds to touch, the DC bias provided by the PIC may be wrong. Try adding large-value resistance connected between oscillator pins (10Meg, even 22Meg.)

It's possible that your crystal could be damaged by overdrive. (One ref suggests including over 100K of resistance between SOSC pin and the crystal.)

For lots of info, read spec sheets for older chips with oscillators using these low-freq tuning-fork crystals...

http://www.ti.com/lit/an/slaa322d/slaa322d.pdf

PS I notice that electronic goldmine currently has cheap "watch crystals" tuning forks with unusual frequencies, not 32KHz

• Agree. Most 32 kHz crystal oscillators I've seen need the 10 MEG resistor across the crystal pins. – Vince Patron Aug 15 '17 at 0:37
• True since square wave symmetry is balanced by Vgs crossover threshold near Vdd/2. But incorrect since Microchip already includes 10M and recommend 1M for 32k devices externally in one of fheir App notes – Tony Stewart Sunnyskyguy EE75 Aug 21 '17 at 18:22

In my experience and most OEM's such TI, recommend 1MOhm external feedback , not 10M which already inside. Tuning fork resonators have high ESR and have much lower uW damage thresholds than XT mode or AT cut crystals.

.warning. If you ignore Mfg or OEM App Notes it may be damaged.

This is a parallel resonant circuit. The resonance is high impedance 180 degree phase shift which after inversion gives positive feedback. Internally there is 10M ohm high R feedback which at DC serves to self bias the input at Vdd/2 to give a square wave out which has an avg DC voltage of Vdd/2.

If the input DC is not near this value, Vdd/2 where it operates as a linear inverting amplifier, the output will be stuck at "1" or "0" . I would expect 330 ohms between the Input SOSCI and Vss or Vdd to shift the bias enough and stop the clock. This contradicts your tests with 330 Ohm to 0V and only makes sense if you reversed In and Out, as only the output SOSCO, can drive this.

The motional capacitance is only about 3.5 fF (fentofarads) with an inductance of about 35kH and ESR of 35~70 kOhms. This defines the optimal resonator parameters to oscillate at 32768 Hz. The Q is >10k.

• add 1M external feedback to reduce potential errors from surface leakage contamination and mis-bias
• add series R to prevent uW overdrive , eg 10k and testing this for margin with failure to oscillate margin Rs/(sRs+ESR) > 2 = marginal, 3= better, 5= best This ensures there is enough loop gain to oscillate.
• if you use unequal caps, make the input cap smaller to allow for input capacitance.
• clean all pads of flux
• consider a guard gap island around entire cct then a perimeter guard signal or gnd. to reduce finger interference or crosstalk.

Your only major design flaw was the copper fill around all tracks adds too much capacitance and reduces Phase shift feedback from 180 towards 90 deg where if the loop gain is insufficient, it will not oscillate or force a lower resonance. This layout forces you to choose a xtal requiring larger load caps for stability to satisfy Barkhausen criteria.

These track gaps ought to be same or no less than the gaps between IC pads as stray C gnd is inverse to gap.

Although Microchip's advice improves margin, they did not anticipate users who use aggressive copper fill gaps < 0.1mm.

The 1:1 probe has too much ground inductance and coax capacitance and 1M will also upset input DC bias.