# Basic questions regarding Push Pull stage

I am confused as to how the following circuit will work(????)

Lets assume that there is no AC signal and only a DC signal is applied.

1. According to the books this is a voltage follower stage i.e Vo will be equal to Vi. But how is that possible? Both the transistors are always in cut off because Vgs of NMOS and PMOS should be zero and hence Vo should be floating. But if I sweep Vi from 0 to Vdd then I also see Vo following Vi. How is the output voltage Vo so well defined?

2. Intuitively this circuit makes no sense to me at all. It would be really nice if someone could explain me in simple words!

EDIT: I will try to explain what i think should happen. For the circuit exactly as described in the picture (no load condition and only DC condition)

1. When Vi is open or gate terminals are floating, with Vdd applied, Vo is floating.

2. When the gate terminals are connected to Vi, and Vi = 0 volts, Vo is still floating (considering Vo_floating > 0 volts is most likely, than Vo = 0 volts), VgsPMOS = negative voltage, hence PMOS will pull Vo to ground. 2.1: If Vo_floating = exactly 0 Volts (Vo=Vi) then it is the same case as 2.

3. When Vi > 0 but less than Vth(PMOS and NMOS) VgsNMOS = +ve and VgsPMOS = -ve (since Vo >=0), Vo = 0 volts

4. Vi > Vth but Vi << Vdd imples, VgsNMOS > VthNMOS and -VgsPMOS < -VthPMOS, hence both the transistors are conducting. VgsNMOS = Vi-Vo, hence Vo=Vi-VgsNMOS. However at this stage Vo = IdRdsPMOS, where Id is the drain current that will be defined by VgsNMOS (Id = gmVgsNMOS).If RdsPMOS is very high then Vo will increase reducing VgsNMOS. But what if VgsNMOS drop below Vth? Why cant this happen? What will define Vo (is it Vo=Vi-VgsNMOS? or Vo = Id*RdsPMOS?) here and why?

• This looks like an inverter... or a NOT gate...
– user103380
Aug 14, 2017 at 16:02
• @KingDuken but it is not the inverter. It is a push-pull stage. A complementary source follower.
– G36
Aug 14, 2017 at 16:06
• @KingDuken, Inverter would have the PMOS and NMOS switched. Aug 14, 2017 at 16:06
• Can you show your simulation result? What is the Vgs(th) in your MOSFET models? Did your model include a load? Aug 14, 2017 at 16:07
• Also, have you studied the BJT class-B amplifier, and understand how it works? This works about the same but typically with worse crossover distortion because the FET Vgs(th) is higher than a BJT's Vbe(on). Aug 14, 2017 at 16:08

Let's look at a BJT version, and I'll also include a load on the output:

simulate this circuit – Schematic created using CircuitLab

Now does it make more sense?

When the input voltage is higher than ground (or whatever the load terminates to), then the b-e junction of Q1 will be forward biased, and Q1 will conduct into the load. At the same time, Q2's b-e will be reverse biased, so Q2 will be in cut off.

When the input voltage is below ground (or whatever the load terminates to), Q2 will be forward active and Q1 will be cut off.

There will be a small region, when the input is within about 0.6 or 0.7 V of ground, where neither Q1 nor Q2 will be turned on, and this will cause the infamous cross-over distortion that we usually talk about when we discuss this circuit.

The MOSFET version you presented will work the same, but because a typical MOSFET Vgs(th) is higher than Vbe(on) of a BJT, the cross-over distortion region will be much wider.

In a single-supply circuit like yours, if the load terminates to ground there is no need to include Q2 (or the PMOS in your circuit), since only Q1 will ever be active. But if you have a load that terminates to an intermediate voltage (or you bias the output there and capacitively couple to the actual load), it could make sense to use this design in a single supply environment

Edit

For the circuit exactly as described in the picture (no load condition and only DC condition) ...

1. When Vi is open or gate terminals are floating, with Vdd applied, Vo is floating.

You can't count on this. Some static charge will likely accumulate on the gate node and drive it upredictably high or low. You should always connect CMOS gates to a known potential.

In the rest of your analysis, you are neglecting that there will be leakage currents through the FET channels and body diodes, so the output voltage will never be truly floating.

Therefore, your expectation that "Vo_floating = exactly 0 Volts" is very unlikely. More likely it will tend toward some voltage near (within a few volts of) Vdd/2. The value will likely change with temperature, passing air currents, etc.

If the input voltage is different from this (varying) value by more than the Vgs(th) of one of the FETs, then it will start to drive the output voltage like a follower circuit. Some charge will accumulate on the output node due to parasitic capacitance. If the input voltage then changes again, it may take some time for the leakage to discharge this capacitance and restore the equilibrium output voltage.

But really, why would you want to use this circuit with no load attached? The whole point of the design is to be able to source or sink relatively large currents into (or out of) a load.

• Note: Perhaps with a capacitive load, Q2 could be useful in a single-supply amplifier with ground-terminated load. Aug 15, 2017 at 1:18
• Hi, this circuit makes sense to me, yes. But what happens if there is no load connected at the common emitter terminal of both the transistors? In your case the emitter terminal is pulled down to ground through Rload. Hence when the input terminal (Vb) is greater than Vbe(on) and since Ve pulled down, Vbe=Vb-Ve> Vbe(on), Q1 will conduct. But if there is no load, then Ve will be floating right? Maybe I need to rephrase my question.
– RAN
Aug 15, 2017 at 11:57
• If there is no load, then leakage currents through the output devices will affect the output. You are right that in the case of the MOS version, there will be a substantial input voltage range where the output is uncertain. Notice the same thing is true about the single-transistor common-collector/common-drain amplifier. Aug 15, 2017 at 14:17
• But why use such a driver stage if your system has no load? Aug 15, 2017 at 14:17
• This is for my understanding of working of MOSFETs. Kindly check the edit which i have posted to the original question.
– RAN
Aug 15, 2017 at 14:20

According to the books this is a voltage follower stage i.e Vo will be equal to Vi

No, Vo will never attain the level of Vi because of loading effects on the output and the need to exceed the gate threshold voltages to be able to turn on (to any reasonable extent) either transistor.

So, if Vi is 5 volts p-p and the power rail is 5 volts, then I would expect to see maybe 4 to 4.5 volts p-p coming out in no load conditions. Why not 5 volts p-p you might ask - the transistor that is "off" will still draw several nano amps and have capacitance from drain the source and this means real current has to pass through the "on" transistor to deal with the loading effect of the "off" transistor. This means the source cannot truly follow the gate without some volt drop.

To better understand this circuit get rid of the P channel MOSFET and replace it with a resistor to form a source follower amplifier - gain is somewhat less than 1 and this is the same basic problem that is faced in the push-pull version (but it is slightly improved in no-load scenarios).

• Hi, I cannot remove the PMOS because that is a problem i am working on. I agree Vo will never attain the voltage of Vi, but it will follow closely. Lets only consider DC condition. If a Vin is applied, then at that moment, Vo will be floating (i hope i am correct). Now I start increasing Vin (not Vgs) so the gate voltage of both transistors start to rise. However Vgs will still remain undefined because the source voltage or Vo is still undefined. Now atleast one of the transistors should come out of CUT OFF to give a definite voltage level to Vo. Which one and why?
– RAN
Aug 14, 2017 at 16:10
• I meant to get rid of the PMOS as a thought experiment. At the point you connect 0 volts to Vi you are turning the NMOS off as much as is physically possible but the PMOS can turn on - remember these MOSFETs are not perfect and there will be several nano amps flowing through them under static situations. This will cause the output voltage to drop towards 0 volts because the P channel MOSFET has been given the best input voltage (0 volts in this case) to turn a little bit on. Aug 14, 2017 at 16:15
• When you put 5 volts on the gates you get the reverse situation - the PMOS has no chance of turning on but will still provide several nano amps to the NMOS thus pulling down the NMOS source a little bit and giving the NMOS a real gate-source voltage by which it will cause a little conduction. Aug 14, 2017 at 16:18
• Isnt the best input to PMOS gate not 0 volts but actually negative with respect to the source?
– RAN
Aug 14, 2017 at 22:42
• The source will always be slightly positive with respect to the gate for a PMOS when that MOSFET is being activated. If you can drive the gate negative below the 0 volts power rail then that ensures the source pulls down to 0 volts. Aug 15, 2017 at 7:14