I'm working on a high speed board design containing transimpedance amplifiers. Here's the schematic below:


simulate this circuit – Schematic created using CircuitLab

Right now, my layout seems fine, but I'm concerned about placing vias to connect ground planes. This is a 6-layered board, with all planes designated as ground planes. I was told that you should place ground vias to connect the ground planes together in order to create a stronger connection to ground between all the layers and/or possibly reduce the inductance of the overall board to allow for faster signaling. Given the layout limitations, the image below showcases the board thus far:


Does the size of the via really matter, or is it better to just have as many vias as possible wherever you can? Are there some recommended areas where I should place more vias? Is this perhaps overkill with the vias? I'm using a coaxial connector for the output of the signal, so I placed tiny vias around it close to the no fill zones.

EDIT: Here's another picture of the board, but horizontal rather than vertical. I apologize for the quality of the image. I can't seem to do any better. The ground vias are completely surrounded by the ground planes (in the images, only the top and bottom ground planes are shown to make it less confusing). You can see an example of them at the coaxial connector, with the center pin surrounded by the no fill zone in the bottom plane. The four ground connectors surrounding it are filled by the ground plane while the center pin doesn't touch it. I don't know if this is a good explanation, but please let me know if I can be clearer about it. Other examples of ground vias include the square of vias in the center of the board.


EDIT: Someone mentioned that it would probably be clearer if I posted the board as separate layers for easier viewing:

Top layer:


Inner Layer 1:

Inner Layer 1

Inner Layer 2:

Inner Layer 2

Inner Layer 3:

Inner Layer 3

Inner Layer 4:

Inner Layer 4

Bottom Layer:

Bottom Layer

  • \$\begingroup\$ Might want to upload a larger image, one in which we can see the vias. \$\endgroup\$ – Tom Carpenter Aug 14 '17 at 18:26
  • \$\begingroup\$ You should provide a schematic. Also, please give separate pictures of each layer, that should be a lot more readable... \$\endgroup\$ – peufeu Aug 14 '17 at 18:46
  • 1
    \$\begingroup\$ To me the number of vias is either fine or overkill. I'd bet that if you made 2 versions of this PCB, one like shown and one where you remove half of the vias, you would be unable to distinguish between them in a measurement. You write "high speed" but we're the opamp is a 500 MHz one so it's not like we're in the GHz range. \$\endgroup\$ – Bimpelrekkie Aug 14 '17 at 18:47
  • \$\begingroup\$ Does the size of the via matter? \$\endgroup\$ – user101402 Aug 14 '17 at 18:50

Does the size of the via really matter, or is it better to just have as many vias as possible wherever you can? Are there some recommended areas > > > where I should place more vias?

The size of the via matters, because it changes the value of inductance and resistance. Go find a PCB trace\via calculator. I get lower values of inductance with a larger radius (probably because the current is spread out). Vias can be 1 to 10nH. They also have a charateristic impedance so you can get reflections and in high frequency designs, they need to be matched.

Each piece of copper can be modeled with resistance and inductance. There exists mutual coupling between currents via magnetic fields on a PCB which can be modeled as mutual inductance. Electric fields between conductors can be modeled as capacitance. There are calculators available and papers on how to model these effects. Once you have a value for inductance, resistance and\or capacitance, you can model this in your circuit diagrams and hand calculations or in a spice package.

Is this perhaps overkill with the vias? I'm using a coaxial connector for the output of the signal, so I placed tiny vias around it close to the no fill zones.

If your intention is to provide a path for return current between planes then probably not. High frequency currents take the path of lowest impedance. Adding more vias is paralleling the inductance which will lower it if that is your objective. Realize that there is also inductance between vias from the copper itself, eventually adding more vias will have diminishing returns as most of the current will take the first few rows of vias. Place vias close to the source to minimize inductance from planes and traces when connecting planes or providing paths for return currents.

  • \$\begingroup\$ Currents at all frequencies always take all possible paths, proportional to conductance. There is no truth to "high frequency currents take the path of lowest impedance." \$\endgroup\$ – analogsystemsrf Aug 16 '17 at 5:03
  • \$\begingroup\$ Sorry, I was just quoting this guy, you can argue with him about it. Most of the other paths are much higher impedance, so 99% of the current goes down one path. It's a general rule to remember, I like it a lot, Its helped me out more than once. \$\endgroup\$ – Voltage Spike Aug 16 '17 at 5:04

The density you need to place stitching vias is related to the frequency content of the signals in your circuit. If the maximum frequency in the circuit is 500 MHz (corresponding to roughly 30 cm wavelength in FR4), then I'd expect that if the stitching vias are spaced no further than 3 cm apart you'll be fine.

On your very small board, this probably means that 4 or 8 vias around the board will be fine.

Does the size of the via matter?

Larger vias have lower resistance. Very small vias may be more costly to produce (because the drills break more frequently). Typically this is not a critical issue for stitching vias in the sub-GHz frequencies.


Difficult to give a specific answer to a general question, so use these guidelines:

  • Never insert vias when you have a differential pair
  • If you must insert a via, do the same for both traces
  • If that is not possible, you will need to compensate for added LCR delay
  • Vias can cause reflections
  • Place gnd vias around signal vias to shorten current return path
  • Don't put the vias very close so there would be some ground between them
  • \$\begingroup\$ Thank you for your guidelines. I don't have a differential pair in my circuit, so that's no problem. It's just a simple transimpedance amplifier in an inverting mode. I placed as many GND vias as I could around signal vias, but since they are GND vias, would they be fine if the vias were close together (the GND vias, not GND via and signal)? Also, even though they are GND vias, would they still cause reflection? If so, would it be better to designate them as No-Connect so they don't connect to anything? \$\endgroup\$ – user101402 Aug 14 '17 at 18:49
  • \$\begingroup\$ I think the question is about ground-stitching vias, not vias in signal paths. \$\endgroup\$ – The Photon Aug 14 '17 at 19:07

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