To my understanding both pipelining and caching make use of memory to reduce the amount of idle hardware.
I am considdering a project that has multiple input data streams with a slow clock rate, which are transmitted to data processors at a higher clock rate using an asynchronous FIFO IP core.
Each data processor is assigned to multiple data streams, but it does not have access to the data streams from other data processors.
Is this called caching or pipelining? (I'm for caching, but I would like to be sure)...