Is it possible for (W/L) of 0.18nm PMOS to become 989100 ? If not,i wonder what the range is for (W/L) of TSMC 0.18nm PMOS and NMOS.Thanks a lot.
Theoretically you can make any W/L you want. But as the ratio gets higher you might want to look for alternative plans, such as transistors in parallel.
I'm assuming you mean a 0.18 um process since I don't believe TSMC, or anyone, has a 0.18 nm process. If so a W/L of 989100 and L = 0.18 um would give you a width of 17.8 cm. This is a bit absurd and would make for a very large, or strangely shaped, die. Both of which I'm sure you would want to avoid.
TSMC published rules for their different processes. It is likely that the maximum dimensions are provided there. If not, then I would assume they define no limits and if you are okay with the die size, then you can go for it.
When designing a circuit with FETs you can generally make any W/L you want, but as I mentioned earlier, this might make the dimensions of your FETs undesirable. You can instead replace a FET of width
W with the parallel combination of
n FETs of width
W/n as shown:
In this image, all three combinations of FETs "should" work the same. There will be some slight differences between these designs that I'm ignoring, but they should be relatively minor.
\$\begingroup\$ Can you take some cases about transistors in parallel for example?Thx \$\endgroup\$ Aug 15, 2017 at 4:54
\$\begingroup\$ @蕭仰恩 I think that should help clear things up. \$\endgroup\$– MattAug 15, 2017 at 15:02