I'm looking at the ATMega328 datasheet and the Arduino UNO Wire/twi implementation, as well as a logic analyzer trace of a proprietary device I'm trying to send data to.
The device is trying to read anywhere from N=48 to 512 bytes. It keeps driving the clock for N packets (8-bits+ACK), but the UNO stack's interrupt only sends 32 bytes per transaction.
The spec leads me to believe that the master should NACK when it is done, but the wire code in the UNO lib state machine (for slave transmit) drives ACK/NACK when there is still data left.
This isn't clear to me: who drives ACK/NACK on the 9th bit during a slave transmit?