I have read some articles about USB2.0 where the maximum skew for the differential pair is given; it can then be derived the maximum length difference between two traces of a pair.
However, I looked for similar specifications in the Zynq documentation without success, so I went more into the current design on the demo board. 6 LVDS pairs goes from the camera to the Zynq (4 data, 1 clock, 1 sync). Internal terminations from the Zynq are used for differential pairs. The Avnet IP to connect the Python 1300 to the Zynq uses 3 primitives for the data channels:
I found some info about the setup and hold time for the ISERDESE2 primitive:
My guess is that the length difference tolerance within a pair can be derived from the setup and hold time of the ISERDESE2 primitive, and the IDELAYE2 is there to compensate for the length difference between pairs. However, I do not understand how I can derive a timing budget based on these information.
Could anyone give me some hints to better understand how to calculate the length matching tolerances in this scenario? Rule of thumbs are also welcome.