0
\$\begingroup\$

I'm interested in the LVDS communication between a Zynq (Xilinx, xc7z020-1C) and a camera (ON semiconductor Python 1300 NOIP1SE1300A−QDI).

I have read some articles about USB2.0 where the maximum skew for the differential pair is given; it can then be derived the maximum length difference between two traces of a pair.

However, I looked for similar specifications in the Zynq documentation without success, so I went more into the current design on the demo board. 6 LVDS pairs goes from the camera to the Zynq (4 data, 1 clock, 1 sync). Internal terminations from the Zynq are used for differential pairs. The Avnet IP to connect the Python 1300 to the Zynq uses 3 primitives for the data channels:

  • IBUFDS
  • IDELAYE2
  • ISERDESE2

I found some info about the setup and hold time for the ISERDESE2 primitive:

Iserdese2 in Zynq 7020

My guess is that the length difference tolerance within a pair can be derived from the setup and hold time of the ISERDESE2 primitive, and the IDELAYE2 is there to compensate for the length difference between pairs. However, I do not understand how I can derive a timing budget based on these information.

Could anyone give me some hints to better understand how to calculate the length matching tolerances in this scenario? Rule of thumbs are also welcome.

Thank you

\$\endgroup\$
3
\$\begingroup\$

Trace length equalization for a differential pair is not determined by setup/hold timing. It is determined by having a crossover point of eye diagram in right place, to keep it in the middle. The allowable timing skew therefore depends on reasonable slew rate of signal edges.

As I understand, the camera max frequency is 720 mbps, or 1380 ps of unit interval. Therefore the edge rate can be about 400 ps, so 100 ps difference wouldn't make much of a shift in eye crossover position. And the 100ps would be equal to 15-20 mm in trace length difference, which is huge. So the diff. pair length equalization to 2-3mm is not an issue.

Regarding the parallel channels and IOBUF programmable delay, I believe Xilinx has it in 15ps-something granularity (x256), so almost any reasonable trace difference can be tuned up and corrected in RTL.

\$\endgroup\$
  • \$\begingroup\$ Thank you! If I understand correctly, the allowing timing skew does not depend on parameters of the receiver. I'm wondering how you actually estimate the rising edge and falling edge for a given frequency? Is it some rules of thumb? \$\endgroup\$ – Marmoz Aug 24 '17 at 13:19
  • 1
    \$\begingroup\$ @Marmoz, high-speed communication lanes are designed/defined to limit unnecessary high-frequency content of signals (to reduce cross-talk and EMI), and the edge rates are defined as just short enough to switch between Low and High logic states. It is sufficient to have 1/3 of UI in final state (H/L) and 1/3 for both edges. Sine waveform would be preferable, but difficul to achieve, so the rule of 1/3 is good enough. See some examples of eye diagrams here, testusb.com/HSEYE.htm or here teledynelecroy.com/images/serialdata/qphy-usb3-tx-rx-03.png \$\endgroup\$ – Ale..chenski Aug 24 '17 at 17:43
  • \$\begingroup\$ You really made my day with your comment! This 1/3 rule makes a lot of sense :) \$\endgroup\$ – Marmoz Aug 24 '17 at 20:07

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.