Lets say I want to realize a logic function in CMOS gates.

I have a function like this $$Y = (¬A *¬B) + ¬C + ¬D$$

If I had a function without inverted inputs: $$ Y = ( A*B) +C +D $$ it does not present a challenge to me but with the inverted inputs this is much harder for me.

What do I have to do to model these functions with CMOS gates ?

  • \$\begingroup\$ How does this differ from any other technology mapping? And what makes the non-inverting one any easier? If you can do the non-inverting one, then you should easily be able to do the other as well, as inverters are the most elementary building block in a CMOS process. \$\endgroup\$
    – Joren Vaes
    Aug 21, 2017 at 9:58
  • \$\begingroup\$ well but then I'd have a non minimal solution if I use 2 transistors for every input, I suspect this can be done more efficiently \$\endgroup\$
    – zython
    Aug 21, 2017 at 10:01
  • \$\begingroup\$ Inverted inputs turn on the P transistors within a gate, directly implementing your transfer function. I believe you have made a mistake in the second function. \$\endgroup\$
    – RoyC
    Aug 21, 2017 at 10:25
  • \$\begingroup\$ the second function was just an example, it has no relation to the first function, but do you mean if I had no negation I would just use n transistors ? \$\endgroup\$
    – zython
    Aug 21, 2017 at 10:33

1 Answer 1


Well, in CMOS usually all functions are inverting. The most simple logic function you can implement is a NAND or a NOR (besides the inverter).

OR an AND Gates in cmos logic are basically NOR and NAND with an inverter behind.

Use De Morgan's law (https://en.wikipedia.org/wiki/De_Morgan%27s_laws) and the rules of boolean algebra to convert your formula:



Now it depends on your hardware constraints, if you want to have a solution with minimal gates or with more gates but a smaller "fan in" (more input gates make your circuit slower).

A solution with minimal fan in would be


simulate this circuit – Schematic created using CircuitLab

This can be translated to cmos 1:1 by using the standard layout for cmos gates.

Now if you want to have a single gate, it gets trickier. Convert the formula one step further to get an inversion as the outermost operator: $$Y=¬((A+B)*(C*D))$$

You can see that the basic structure is a NAND gate. Now you have to design the pull up network and the pull down network.

For the pull down network, an AND in the logical formula means to connect the transistors in series and for an OR you have to connect them in parallel. For the pull up network it is vice versa.

The pull down network would look like this:


simulate this circuit

And complementary the pull up network:


simulate this circuit

Now combine them and you are done. If you have inverted inputs in the last formula, you have to invert the inputs with an separate inverter before connecting them to the gate.

  • \$\begingroup\$ makes sense, accepted \$\endgroup\$
    – zython
    Aug 21, 2017 at 12:54

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